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/Zephyr-latest/tests/drivers/can/api/src/
Dcommon.h5 * SPDX-License-Identifier: Apache-2.0
33 * @brief Standard (11-bit) CAN IDs and masks used for testing.
43 * @brief Extended (29-bit) CAN IDs and masks used for testing.
61 * @brief Standard (11-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID frame 2.
71 * @brief Extended (29-bit) CAN ID frame 1.
76 * @brief Extended (29-bit) CAN ID frame 1.
81 * @brief Standard (11-bit) CAN ID RTR frame 1.
86 * @brief Extended (29-bit) CAN ID RTR frame 1.
92 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
[all …]
Dcommon.c5 * SPDX-License-Identifier: Apache-2.0
26 * @brief Standard (11-bit) CAN ID frame 1.
36 * @brief Standard (11-bit) CAN ID frame 2.
46 * @brief Extended (29-bit) CAN ID frame 1.
56 * @brief Extended (29-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID RTR frame 1.
76 * @brief Extended (29-bit) CAN ID RTR frame 1.
87 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
93 .data = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
101 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
[all …]
Dutilities.c5 * SPDX-License-Identifier: Apache-2.0
35 zassert_equal(can_dlc_to_bytes(11), 20, "wrong number of bytes for DLC 11"); in ZTEST()
57 zassert_equal(can_bytes_to_dlc(20), 11, "wrong DLC for 20 bytes"); in ZTEST()
75 /* Standard (11-bit) frames and filters */ in ZTEST()
85 /* Extended (29-bit) frames and filters */ in ZTEST()
95 /* Standard (11-bit) frames and extended (29-bit) filters */ in ZTEST()
102 /* Extended (29-bit) frames and standard (11-bit) filters */ in ZTEST()
/Zephyr-latest/dts/bindings/sensor/
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
43 1 = /2 -> ±80 mV
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/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
43 IPC_EVENT_BIT(11) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_tach.h4 * SPDX-License-Identifier: Apache-2.0
22 #define MCHP_TACH_CTRL_EXCEED_LIM_EN BIT(0)
26 #define MCHP_TACH_CTRL_EN BIT(MCHP_TACH_CTRL_EN_POS)
30 #define MCHP_TACH_CTRL_FILTER_EN BIT(MCHP_TACH_CTRL_FILTER_EN_POS)
35 #define MCHP_TACH_CTRL_READ_MODE_100K_CLOCK BIT(10)
38 #define MCHP_TACH_CTRL_NUM_EDGES_POS 11
40 #define MCHP_TACH_CTRL_NUM_EDGES_MASK SHLU32(0x03U, 11)
42 #define MCHP_TACH_CTRL_EDGES_3 SHLU32(1u, 11)
43 #define MCHP_TACH_CTRL_EDGES_5 SHLU32(2u, 11)
44 #define MCHP_TACH_CTRL_EDGES_9 SHLU32(3u, 11)
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/Zephyr-latest/drivers/can/
DKconfig.stm324 # Copyright (c) 2018-2020 Alexander Wachter
5 # SPDX-License-Identifier: Apache-2.0
18 int "Maximum number of standard (11-bit) ID filters"
22 Defines the maximum number of filters with standard ID (11-bit)
34 int "Maximum number of extended (29-bit) ID filters"
38 Defines the maximum number of filters with extended ID (29-bit)
62 int "Maximum number of standard (11-bit) ID filters"
66 Defines the maximum number of filters with standard ID (11-bit)
70 int "Maximum number of extended (29-bit) ID filters"
74 Defines the maximum number of filters with extended ID (29-bit)
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
28 /* 32-bit word 1 (bits[63:32]) */
43 /* 32-bit word 2 (bits[95:64]) */
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
78 /* 32-bit word 0 (bits[31:0]) */
96 #define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS)
98 #define ESPI_S2MW0_CHG1 BIT(ESPI_S2MW0_CHG1_POS)
100 #define ESPI_S2MW0_CHG2 BIT(ESPI_S2MW0_CHG2_POS)
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Dmec172x_gpio.h4 * SPDX-License-Identifier: Apache-2.0
54 /* bit[8] output buffer type: push-pull or open-drain */
56 #define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS)
57 #define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS)
60 /* bit[9] direction */
62 #define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS)
63 #define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS)
67 * bit[10] Alternate output disable. Default==0(alternate output enabled)
68 * GPIO output value is controlled by bit[16] of this register.
69 * Set bit[10]=1 if you wish to control pin output using the parallel
[all …]
Dmec172x_pcr.h4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
[all …]
Dmec172x_i2c_smb.h4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
[all …]
/Zephyr-latest/drivers/sensor/ti/tmp116/
Dtmp116.h4 * SPDX-License-Identifier: Apache-2.0
30 #define TMP116_CFGR_AVG (BIT(5) | BIT(6))
31 #define TMP116_CFGR_CONV (BIT(7) | BIT(8) | BIT(9))
32 #define TMP116_CFGR_MODE (BIT(10) | BIT(11))
33 #define TMP116_CFGR_DATA_READY BIT(13)
34 #define TMP116_EEPROM_UL_UNLOCK BIT(15)
35 #define TMP116_EEPROM_UL_BUSY BIT(14)
38 #define TMP116_AVG_8_SAMPLES BIT(5)
39 #define TMP116_AVG_32_SAMPLES BIT(6)
40 #define TMP116_AVG_64_SAMPLES (BIT(5) | BIT(6))
[all …]
/Zephyr-latest/drivers/sensor/ti/fdc2x1x/
Dfdc2x1x.h4 * SPDX-License-Identifier: Apache-2.0
75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1)
85 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_MSK BIT(13)
88 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_MSK BIT(12)
91 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_MSK BIT(11)
92 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_SET(x) (((x) & 0x1) << 11)
93 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_GET(x) (((x) >> 11) & 0x1)
94 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_MSK BIT(5)
97 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_MSK BIT(0)
105 #define FDC2X1X_CFG_SLEEP_SET_EN_MSK BIT(13)
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/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h4 * SPDX-License-Identifier: Apache-2.0
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/include/zephyr/arch/x86/
Dmsr.h3 * SPDX-License-Identifier: Apache-2.0
16 #define X86_SPEC_CTRL_MSR_IBRS BIT(0)
17 #define X86_SPEC_CTRL_MSR_SSBD BIT(2)
20 #define X86_APIC_BASE_MSR_X2APIC BIT(10)
23 #define X86_MTRR_DEF_TYPE_MSR_ENABLE BIT(11)
28 #define X86_EFER_MSR_SCE BIT(0)
29 #define X86_EFER_MSR_LME BIT(8)
30 #define X86_EFER_MSR_NXE BIT(11)
54 * z_x86_msr_write() is shared between 32- and 64-bit implementations, but
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-npm1300-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM1300-specific GPIO Flags
11 * @defgroup gpio_interface_npm1300 nPM1300-specific GPIO Flags
16 * - Bit 8: Drive strength (0=1mA, 1=6mA)
17 * - Bit 9: Debounce (0=OFF, 1=ON)
18 * - Bit 10: Watchdog reset (0=OFF, 1=ON)
19 * - Bit 11: Power loss warning (0=OFF, 1=ON)
91 #define NPM1300_GPIO_PWRLOSSWARN_OFF (0U << 11U)
93 #define NPM1300_GPIO_PWRLOSSWARN_ON (1U << 11U)
Dadi-max32-gpio.h2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
10 * @brief MAX32-specific GPIO Flags
11 * @defgroup gpio_interface_max32 MAX32-specific GPIO Flags
23 * - Bit 8: GPIO Supply Voltage Select
28 * - Bit 9: GPIO Drive Strength Select,
34 * - Bit 10: Weak pull up selection, Weak Pullup to VDDIO (1MOhm)
38 * - Bit 11: Weak pull down selection, Weak Pulldown to VDDIOH (1MOhm)
62 #define MAX32_GPIO_WEAK_PULL_DOWN_POS (11U)
/Zephyr-latest/dts/bindings/dma/
Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
28 0x1: Half-word (16 bits)
31 -bit 13-14 : Memory data size
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_ace_v1x_art_regs.h4 * SPDX-License-Identifier: Apache-2.0
22 #define ACE_TSCTRL_ODTS_MASK BIT(5)
23 #define ACE_TSCTRL_LWCS_MASK BIT(6)
24 #define ACE_TSCTRL_HHTSE_MASK BIT(7)
25 #define ACE_TSCTRL_CLNKS_MASK GENMASK(11, 10)
27 #define ACE_TSCTRL_IONTE_MASK BIT(30)
28 #define ACE_TSCTRL_NTK_MASK BIT(31)
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v2_internal.h4 * SPDX-License-Identifier: Apache-2.0
9 #define AUX_MPU_EN_ENABLE BIT(30)
10 #define AUX_MPU_EN_DISABLE ~BIT(30)
13 * The size of the region is a 5-bit field, the three MSB bits are
14 * represented in [11:9] and the two LSB bits are represented in [1:0].
16 * 00000-00011 Reserved
25 * Bit ... 12 11 10 9 8 3 2 1 0
26 * ------+------------+------+---+-----------+
27 * ... | SIZE[11:9] | ATTR | R | SIZE[1:0] |
28 * ------+------------+------+---+-----------+
[all …]
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dcpu.h3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
16 * SCTLR register bit assignments
49 #define DFSR_WRITE_MASK (1 << 11)
52 /* Armv8-R AArch32 architecture profile */
54 #define SCTLR_M_BIT BIT(0)
55 #define SCTLR_A_BIT BIT(1)
56 #define SCTLR_C_BIT BIT(2)
57 #define SCTLR_I_BIT BIT(12)
59 /* Armv8-R Cortex-R52 Cache Segregation Control Register */
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