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/Zephyr-latest/arch/arm64/core/
Duserspace.S29 mov x0, #0
30 mov x4, #0
47 mov x0, #0
75 tbnz x4, #0, abv_fail
81 mov x0, #0
107 ldr x9, =K_SYSCALL_LIMIT
108 cmp x8, x9
116 ldr x9, =_k_syscall_table
117 ldr x9, [x9, x8, lsl #3]
121 blr x9
Dcoredump.c30 uint64_t x9; member
68 (void)memset(&arch_blk, 0, sizeof(arch_blk)); in arch_coredump_info_dump()
83 arch_blk.r.x9 = esf->x9; in arch_coredump_info_dump()
Dearly_mem_funcs.S26 tst x0, #0x7
34 and x8, x1, #0xff
35 mov x9, #0x0101010101010101
36 mul x8, x8, x9
60 tst x8, #0x7
Dreset.S91 msr SPSel, #0
122 msr DAIFSet, #0xf
160 mov x5, #0
199 * Initialize the interrupt stack with 0xaa so stack utilization
206 sub x9, sp, #8
207 mov x10, 0xaaaaaaaaaaaaaaaa
209 cmp x0, x9
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg24-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
39 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
43 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
[all …]
Dxg23-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
39 #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
44 #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
[all …]
/Zephyr-latest/samples/modules/canopennode/objdict/
Dobjdict.eds17 VendorNumber=0
19 ProductNumber=0
20 RevisionNumber=0
29 SimpleBootUpMaster=0
30 SimpleBootUpSlave=0
31 Granularity=0
32 DynamicChannelsSupported=0
33 CompactPDO=0
34 GroupMessaging=0
37 LSS_Supported=0
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
[all …]
Dism330dhcx.h10 #define ISM330DHCX_DT_ODR_OFF 0x0
11 #define ISM330DHCX_DT_ODR_12Hz5 0x1
12 #define ISM330DHCX_DT_ODR_26H 0x2
13 #define ISM330DHCX_DT_ODR_52Hz 0x3
14 #define ISM330DHCX_DT_ODR_104Hz 0x4
15 #define ISM330DHCX_DT_ODR_208Hz 0x5
16 #define ISM330DHCX_DT_ODR_416Hz 0x6
17 #define ISM330DHCX_DT_ODR_833Hz 0x7
18 #define ISM330DHCX_DT_ODR_1666Hz 0x8
19 #define ISM330DHCX_DT_ODR_3332Hz 0x9
[all …]
Dlsm6dso.h10 #define LSM6DSO_DT_XL_HP_MODE 0
15 #define LSM6DSO_DT_GY_HP_MODE 0
19 #define LSM6DSO_DT_FS_2G 0
25 #define LSM6DSO_DT_FS_250DPS 0
32 #define LSM6DSO_DT_ODR_OFF 0x0
33 #define LSM6DSO_DT_ODR_12Hz5 0x1
34 #define LSM6DSO_DT_ODR_26H 0x2
35 #define LSM6DSO_DT_ODR_52Hz 0x3
36 #define LSM6DSO_DT_ODR_104Hz 0x4
37 #define LSM6DSO_DT_ODR_208Hz 0x5
[all …]
Dlsm6dso16is.h10 #define LSM6DSO16IS_DT_FS_2G 0
16 #define LSM6DSO16IS_DT_FS_250DPS 0x0
17 #define LSM6DSO16IS_DT_FS_500DPS 0x1
18 #define LSM6DSO16IS_DT_FS_1000DPS 0x2
19 #define LSM6DSO16IS_DT_FS_2000DPS 0x3
20 #define LSM6DSO16IS_DT_FS_125DPS 0x10
23 #define LSM6DSO16IS_DT_ODR_OFF 0x0
24 #define LSM6DSO16IS_DT_ODR_12Hz5_HP 0x1
25 #define LSM6DSO16IS_DT_ODR_26H_HP 0x2
26 #define LSM6DSO16IS_DT_ODR_52Hz_HP 0x3
[all …]
Dtmag5273.h12 #define TMAG5273_DT_OPER_MODE_CONTINUOUS 0
16 #define TMAG5273_DT_AXIS_NONE 0x0
17 #define TMAG5273_DT_AXIS_X 0x1
18 #define TMAG5273_DT_AXIS_Y 0x2
19 #define TMAG5273_DT_AXIS_Z 0x4
24 #define TMAG5273_DT_AXIS_XYX 0x8
25 #define TMAG5273_DT_AXIS_YXY 0x9
26 #define TMAG5273_DT_AXIS_YZY 0xA
27 #define TMAG5273_DT_AXIS_XZX 0xB
30 #define TMAG5273_DT_AXIS_RANGE_LOW 0
[all …]
/Zephyr-latest/soc/neorv32/
Dreset.S17 lui x0, 0
55 la x9, __io_end
56 1: sw x0, 0(x8)
58 bne x8, x9, 1b
/Zephyr-latest/dts/bindings/display/
Dilitek,ili9342c.yaml16 default: [0x01]
23 default: [0x40]
29 default: [0x00]
35 default: [0x00, 0x1c]
41 default: [0x0a, 0x80, 0x1d, 0x04]
44 default SS bit value (0) may interfere with display rotation.
48 default: [0x07]
54 default: [0x9, 0x9]
60 default: [0x00]
66 default: [0xB2]
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Ddma_smartbond.h17 #define DMA_SMARTBOND_TRIG_MUX_SPI 0x0
18 #define DMA_SMARTBOND_TRIG_MUX_SPI2 0x1
19 #define DMA_SMARTBOND_TRIG_MUX_UART 0x2
20 #define DMA_SMARTBOND_TRIG_MUX_UART2 0x3
21 #define DMA_SMARTBOND_TRIG_MUX_I2C 0x4
22 #define DMA_SMARTBOND_TRIG_MUX_I2C2 0x5
23 #define DMA_SMARTBOND_TRIG_MUX_USB 0x6
24 #define DMA_SMARTBOND_TRIG_MUX_UART3 0x7
25 #define DMA_SMARTBOND_TRIG_MUX_PCM 0x8
26 #define DMA_SMARTBOND_TRIG_MUX_SRC 0x9
[all …]
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_smartbond.h18 DMA_SMARTBOND_TRIG_MUX_SPI = 0x0,
19 DMA_SMARTBOND_TRIG_MUX_SPI2 = 0x1,
20 DMA_SMARTBOND_TRIG_MUX_UART = 0x2,
21 DMA_SMARTBOND_TRIG_MUX_UART2 = 0x3,
22 DMA_SMARTBOND_TRIG_MUX_I2C = 0x4,
23 DMA_SMARTBOND_TRIG_MUX_I2C2 = 0x5,
24 DMA_SMARTBOND_TRIG_MUX_USB = 0x6,
25 DMA_SMARTBOND_TRIG_MUX_UART3 = 0x7,
26 DMA_SMARTBOND_TRIG_MUX_PCM = 0x8,
27 DMA_SMARTBOND_TRIG_MUX_SRC = 0x9,
[all …]
/Zephyr-latest/include/zephyr/arch/arc/v2/
Dexception.h26 #define ARC_EV_RESET 0x0
27 #define ARC_EV_MEM_ERROR 0x1
28 #define ARC_EV_INS_ERROR 0x2
29 #define ARC_EV_MACHINE_CHECK 0x3
30 #define ARC_EV_TLB_MISS_I 0x4
31 #define ARC_EV_TLB_MISS_D 0x5
32 #define ARC_EV_PROT_V 0x6
33 #define ARC_EV_PRIVILEGE_V 0x7
34 #define ARC_EV_SWI 0x8
35 #define ARC_EV_TRAP 0x9
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra.h10 #define RA_PORT_NUM_POS 0
11 #define RA_PORT_NUM_MASK 0xf
14 #define RA_PIN_NUM_MASK 0xf
16 #define RA_PSEL_HIZ_JTAG_SWD 0x0
17 #define RA_PSEL_AGT 0x1
18 #define RA_PSEL_GPT0 0x2
19 #define RA_PSEL_GPT1 0x3
20 #define RA_PSEL_SCI_0 0x4
21 #define RA_PSEL_SCI_2 0x4
22 #define RA_PSEL_SCI_4 0x4
[all …]
/Zephyr-latest/subsys/bluetooth/host/classic/
Davrcp_internal.h12 #define AVCTP_VER_1_4 (0x0104u)
13 #define AVRCP_VER_1_6 (0x0106u)
15 #define AVRCP_CAT_1 BIT(0) /* Player/Recorder */
20 #define AVRCP_SUBUNIT_PAGE (0) /* Fixed value according to AVRCP */
24 BT_AVRCP_CTYPE_CONTROL = 0x0,
25 BT_AVRCP_CTYPE_STATUS = 0x1,
26 BT_AVRCP_CTYPE_SPECIFIC_INQUIRY = 0x2,
27 BT_AVRCP_CTYPE_NOTIFY = 0x3,
28 BT_AVRCP_CTYPE_GENERAL_INQUIRY = 0x4,
29 BT_AVRCP_CTYPE_NOT_IMPLEMENTED = 0x8,
[all …]
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Darm64.py18 X0 = 0 # X0-X29 - 30 GP registers
27 X9 = 9 variable in RegNum
78 self.registers[RegNum.X0] = tu[0]
87 self.registers[RegNum.X9] = tu[9]
110 idx = 0
/Zephyr-latest/tests/arch/riscv/fatal/src/
Dmain.c20 "li x1, 0xDADA0000FF000101\n\t" in main()
23 /* "li x2, 0\n\t" */ in main()
26 "li x5, 0xD0FF0000FF000505\n\t" in main()
27 "li x6, 0xD1FF0000FF000606\n\t" in main()
28 "li x7, 0xD2FF0000FF000707\n\t" in main()
30 "li x8, 0xC0FF0000FF000808\n\t" in main()
31 "li x9, 0xC1FF0000FF000909\n\t" in main()
33 "li x10, 0xA0FF0000FF000A10\n\t" in main()
34 "li x11, 0xA1FF0000FF000B11\n\t" in main()
35 "li x12, 0xA2FF0000FF000C12\n\t" in main()
[all …]
/Zephyr-latest/include/zephyr/drivers/firmware/scmi/
Dpinctrl.h19 #define SCMI_PINCTRL_NO_FUNCTION 0xFFFFFFFF
23 SCMI_FIELD_MAKE(cfg_num, GENMASK(7, 0), 2) | \
24 SCMI_FIELD_MAKE(selector, GENMASK(1, 0), 0))
26 #define SCMI_PINCTRL_SELECTOR_PIN 0x0
27 #define SCMI_PINCTRL_SELECTOR_GROUP 0x1
36 SCMI_PINCTRL_MSG_PROTOCOL_VERSION = 0x0,
37 SCMI_PINCTRL_MSG_PROTOCOL_ATTRIBUTES = 0x1,
38 SCMI_PINCTRL_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
39 SCMI_PINCTRL_MSG_PINCTRL_ATTRIBUTES = 0x3,
40 SCMI_PINCTRL_MSG_PINCTRL_LIST_ASSOCIATIONS = 0x4,
[all …]
Dclk.h17 #define SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK GENMASK(1, 0)
21 #define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0))
39 SCMI_CLK_MSG_PROTOCOL_VERSION = 0x0,
40 SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES = 0x1,
41 SCMI_CLK_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
42 SCMI_CLK_MSG_CLOCK_ATTRIBUTES = 0x3,
43 SCMI_CLK_MSG_CLOCK_DESCRIBE_RATES = 0x4,
44 SCMI_CLK_MSG_CLOCK_RATE_SET = 0x5,
45 SCMI_CLK_MSG_CLOCK_RATE_GET = 0x6,
46 SCMI_CLK_MSG_CLOCK_CONFIG_SET = 0x7,
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f105-pll-clock.yaml28 const: 0
45 - 9 # x9
/Zephyr-latest/arch/arc/include/
Dvector_table.h24 #define EXC_EV_TRAP 0x9

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