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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg22-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
[all …]
Dxg23-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
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Dxg27-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
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Dxg24-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-alts-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common pin-mux configurations in npcx family */
8 #include <nuvoton/npcx/npcx-alts-map.dtsi>
10 /* Specific pin-mux configurations in npcx4 series */
12 npcx-alts-map {
13 compatible = "nuvoton,npcx-pinctrl-conf";
15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x02 0x7 0>;
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/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 npcx-alts-map {
9 compatible = "nuvoton,npcx-pinctrl-conf";
12 /* SCFG DEVALT 0 */
14 alts = <&scfg 0x00 0x0 0>;
16 alt0_gpio_no_spip: alt03-inv {
17 alts = <&scfg 0x00 0x3 1>;
19 alt0_gpio_no_fpip: alt07-inv {
21 alts = <&scfg 0x00 0x7 1>;
26 alts = <&scfg 0x01 0x0 0>;
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/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h4 * SPDX-License-Identifier: Apache-2.0
10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
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Dism330dhcx.h4 * SPDX-License-Identifier: Apache-2.0
10 #define ISM330DHCX_DT_ODR_OFF 0x0
11 #define ISM330DHCX_DT_ODR_12Hz5 0x1
12 #define ISM330DHCX_DT_ODR_26H 0x2
13 #define ISM330DHCX_DT_ODR_52Hz 0x3
14 #define ISM330DHCX_DT_ODR_104Hz 0x4
15 #define ISM330DHCX_DT_ODR_208Hz 0x5
16 #define ISM330DHCX_DT_ODR_416Hz 0x6
17 #define ISM330DHCX_DT_ODR_833Hz 0x7
18 #define ISM330DHCX_DT_ODR_1666Hz 0x8
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Diis2iclx.h4 * SPDX-License-Identifier: Apache-2.0
10 #define IIS2ICLX_DT_FS_500mG 0
16 #define IIS2ICLX_DT_ODR_OFF 0x0
17 #define IIS2ICLX_DT_ODR_12Hz5 0x1
18 #define IIS2ICLX_DT_ODR_26H 0x2
19 #define IIS2ICLX_DT_ODR_52Hz 0x3
20 #define IIS2ICLX_DT_ODR_104Hz 0x4
21 #define IIS2ICLX_DT_ODR_208Hz 0x5
22 #define IIS2ICLX_DT_ODR_416Hz 0x6
23 #define IIS2ICLX_DT_ODR_833Hz 0x7
Dlsm6dso.h4 * SPDX-License-Identifier: Apache-2.0
9 /* Accel power-modes */
10 #define LSM6DSO_DT_XL_HP_MODE 0
14 /* Gyro power-modes */
15 #define LSM6DSO_DT_GY_HP_MODE 0
19 #define LSM6DSO_DT_FS_2G 0
25 #define LSM6DSO_DT_FS_250DPS 0
32 #define LSM6DSO_DT_ODR_OFF 0x0
33 #define LSM6DSO_DT_ODR_12Hz5 0x1
34 #define LSM6DSO_DT_ODR_26H 0x2
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Dlsm6dso16is.h4 * SPDX-License-Identifier: Apache-2.0
10 #define LSM6DSO16IS_DT_FS_2G 0
16 #define LSM6DSO16IS_DT_FS_250DPS 0x0
17 #define LSM6DSO16IS_DT_FS_500DPS 0x1
18 #define LSM6DSO16IS_DT_FS_1000DPS 0x2
19 #define LSM6DSO16IS_DT_FS_2000DPS 0x3
20 #define LSM6DSO16IS_DT_FS_125DPS 0x10
23 #define LSM6DSO16IS_DT_ODR_OFF 0x0
24 #define LSM6DSO16IS_DT_ODR_12Hz5_HP 0x1
25 #define LSM6DSO16IS_DT_ODR_26H_HP 0x2
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-alts-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common pin-mux configurations in npcx family */
8 #include <nuvoton/npcx/npcx-alts-map.dtsi>
10 /* Specific pin-mux configurations in npcx9 series */
12 npcx-alts-map {
13 compatible = "nuvoton,npcx-pinctrl-conf";
15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x05 0x1 0>;
[all …]
/Zephyr-latest/soc/neorv32/
Dreset.S4 * SPDX-License-Identifier: Apache-2.0
17 lui x0, 0
24 /* Disable counter access outside M-mode */
49 csrr x6, mtvec
50 la x7, __dummy_trap_handler
51 csrw mtvec, x7
56 1: sw x0, 0(x8)
61 csrw mtvec, x6
/Zephyr-latest/dts/bindings/dma/
Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
33 3. channel-config: A 32bit mask specifying the DMA channel configuration
35 -bit 0-1 : Direction (see dma.h)
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/Zephyr-latest/drivers/sensor/ti/tmp116/
Dtmp116.h4 * SPDX-License-Identifier: Apache-2.0
12 #define TMP116_REG_TEMP 0x0
13 #define TMP116_REG_CFGR 0x1
14 #define TMP116_REG_HIGH_LIM 0x2
15 #define TMP116_REG_LOW_LIM 0x3
16 #define TMP116_REG_EEPROM_UL 0x4
17 #define TMP116_REG_EEPROM1 0x5
18 #define TMP116_REG_EEPROM2 0x6
19 #define TMP116_REG_EEPROM3 0x7
20 #define TMP117_REG_TEMP_OFFSET 0x7
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/Zephyr-latest/arch/arm64/core/
Dcoredump.c4 * SPDX-License-Identifier: Apache-2.0
27 uint64_t x6; member
28 uint64_t x7; member
68 (void)memset(&arch_blk, 0, sizeof(arch_blk)); in arch_coredump_info_dump()
74 arch_blk.r.x0 = esf->x0; in arch_coredump_info_dump()
75 arch_blk.r.x1 = esf->x1; in arch_coredump_info_dump()
76 arch_blk.r.x2 = esf->x2; in arch_coredump_info_dump()
77 arch_blk.r.x3 = esf->x3; in arch_coredump_info_dump()
78 arch_blk.r.x4 = esf->x4; in arch_coredump_info_dump()
79 arch_blk.r.x5 = esf->x5; in arch_coredump_info_dump()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Ddma_smartbond.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Vendror-specific DMA peripheral triggering sources.
17 #define DMA_SMARTBOND_TRIG_MUX_SPI 0x0
18 #define DMA_SMARTBOND_TRIG_MUX_SPI2 0x1
19 #define DMA_SMARTBOND_TRIG_MUX_UART 0x2
20 #define DMA_SMARTBOND_TRIG_MUX_UART2 0x3
21 #define DMA_SMARTBOND_TRIG_MUX_I2C 0x4
22 #define DMA_SMARTBOND_TRIG_MUX_I2C2 0x5
23 #define DMA_SMARTBOND_TRIG_MUX_USB 0x6
24 #define DMA_SMARTBOND_TRIG_MUX_UART3 0x7
[all …]
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_smartbond.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Vendror-specific DMA peripheral triggering sources.
18 DMA_SMARTBOND_TRIG_MUX_SPI = 0x0,
19 DMA_SMARTBOND_TRIG_MUX_SPI2 = 0x1,
20 DMA_SMARTBOND_TRIG_MUX_UART = 0x2,
21 DMA_SMARTBOND_TRIG_MUX_UART2 = 0x3,
22 DMA_SMARTBOND_TRIG_MUX_I2C = 0x4,
23 DMA_SMARTBOND_TRIG_MUX_I2C2 = 0x5,
24 DMA_SMARTBOND_TRIG_MUX_USB = 0x6,
25 DMA_SMARTBOND_TRIG_MUX_UART3 = 0x7,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/adc/
Dmcux-lpadc.h2 * SPDX-License-Identifier: Apache-2.0
10 #define MCUX_LPADC_CH0A (0x0)
11 #define MCUX_LPADC_CH0B (0x20)
12 #define MCUX_LPADC_CH1A (0x1)
13 #define MCUX_LPADC_CH1B (0x21)
14 #define MCUX_LPADC_CH2A (0x2)
15 #define MCUX_LPADC_CH2B (0x22)
16 #define MCUX_LPADC_CH3A (0x3)
17 #define MCUX_LPADC_CH3B (0x23)
18 #define MCUX_LPADC_CH4A (0x4)
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/Zephyr-latest/include/zephyr/arch/arc/v2/
Dexception.h4 * SPDX-License-Identifier: Apache-2.0
11 * ARC-specific kernel exception handling interface. Included by arc/arch.h.
26 #define ARC_EV_RESET 0x0
27 #define ARC_EV_MEM_ERROR 0x1
28 #define ARC_EV_INS_ERROR 0x2
29 #define ARC_EV_MACHINE_CHECK 0x3
30 #define ARC_EV_TLB_MISS_I 0x4
31 #define ARC_EV_TLB_MISS_D 0x5
32 #define ARC_EV_PROT_V 0x6
33 #define ARC_EV_PRIVILEGE_V 0x7
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32f105-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
13 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
22 compatible: "st,stm32f105-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
28 const: 0
38 Note: For x6.5 multiplier value, please use "mul = <15>;"
40 - 4 # x4
41 - 5 # x5
42 - 6 # x6
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
11 /* All Banks, Offset 0xe: Bank Select Register */
12 #define BSR 0xe
13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
14 #define BSR_IDENTIFY 0x33
17 /* Bank 0, Offset 0x0: Transmit Control Register */
18 #define TCR 0x0
19 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
20 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
22 /* Bank 0, Offset 0x02: EPH status register */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dmchp-xec-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/dt-util.h>
12 #define MCHP_GPIO 0x0
13 #define MCHP_AF0 0x0
14 #define MCHP_AF1 0x1
15 #define MCHP_AF2 0x2
16 #define MCHP_AF3 0x3
17 #define MCHP_AF4 0x4
18 #define MCHP_AF5 0x5
19 #define MCHP_AF6 0x6
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra.h4 * SPDX-License-Identifier: Apache-2.0
10 #define RA_PORT_NUM_POS 0
11 #define RA_PORT_NUM_MASK 0xf
14 #define RA_PIN_NUM_MASK 0xf
16 #define RA_PSEL_HIZ_JTAG_SWD 0x0
17 #define RA_PSEL_AGT 0x1
18 #define RA_PSEL_GPT0 0x2
19 #define RA_PSEL_GPT1 0x3
20 #define RA_PSEL_SCI_0 0x4
21 #define RA_PSEL_SCI_2 0x4
[all …]
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Darm64.py5 # SPDX-License-Identifier: Apache-2.0
18 X0 = 0 # X0-X29 - 30 GP registers
24 X6 = 6 variable in RegNum
25 X7 = 7 variable in RegNum
78 self.registers[RegNum.X0] = tu[0]
84 self.registers[RegNum.X6] = tu[6]
85 self.registers[RegNum.X7] = tu[7]
110 idx = 0
118 # Register not in coredump -> unknown value

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