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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg24-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
39 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
43 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
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Dxg23-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
39 #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
44 #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
[all …]
Dxg21-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1)
29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1)
32 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1)
35 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1)
38 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1)
42 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4)
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Dxg22-pinctrl.h16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
37 #define SILABS_DBUS_EUART0_RX(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 3)
39 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 38, 1, 0, 1)
[all …]
Dxg27-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
40 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
43 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra.h10 #define RA_PORT_NUM_POS 0
11 #define RA_PORT_NUM_MASK 0xf
14 #define RA_PIN_NUM_MASK 0xf
16 #define RA_PSEL_HIZ_JTAG_SWD 0x0
17 #define RA_PSEL_AGT 0x1
18 #define RA_PSEL_GPT0 0x2
19 #define RA_PSEL_GPT1 0x3
20 #define RA_PSEL_SCI_0 0x4
21 #define RA_PSEL_SCI_2 0x4
22 #define RA_PSEL_SCI_4 0x4
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/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h10 #define LSM6DSV16X_DT_FS_2G 0
16 #define LSM6DSV16X_DT_FS_125DPS 0x0
17 #define LSM6DSV16X_DT_FS_250DPS 0x1
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
20 #define LSM6DSV16X_DT_FS_2000DPS 0x4
21 #define LSM6DSV16X_DT_FS_4000DPS 0xc
24 #define LSM6DSV16X_DT_ODR_OFF 0x0
25 #define LSM6DSV16X_DT_ODR_AT_1Hz875 0x1
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
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Dism330dhcx.h10 #define ISM330DHCX_DT_ODR_OFF 0x0
11 #define ISM330DHCX_DT_ODR_12Hz5 0x1
12 #define ISM330DHCX_DT_ODR_26H 0x2
13 #define ISM330DHCX_DT_ODR_52Hz 0x3
14 #define ISM330DHCX_DT_ODR_104Hz 0x4
15 #define ISM330DHCX_DT_ODR_208Hz 0x5
16 #define ISM330DHCX_DT_ODR_416Hz 0x6
17 #define ISM330DHCX_DT_ODR_833Hz 0x7
18 #define ISM330DHCX_DT_ODR_1666Hz 0x8
19 #define ISM330DHCX_DT_ODR_3332Hz 0x9
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Diis2iclx.h10 #define IIS2ICLX_DT_FS_500mG 0
16 #define IIS2ICLX_DT_ODR_OFF 0x0
17 #define IIS2ICLX_DT_ODR_12Hz5 0x1
18 #define IIS2ICLX_DT_ODR_26H 0x2
19 #define IIS2ICLX_DT_ODR_52Hz 0x3
20 #define IIS2ICLX_DT_ODR_104Hz 0x4
21 #define IIS2ICLX_DT_ODR_208Hz 0x5
22 #define IIS2ICLX_DT_ODR_416Hz 0x6
23 #define IIS2ICLX_DT_ODR_833Hz 0x7
/Zephyr-latest/soc/neorv32/
Dreset.S17 lui x0, 0
56 1: sw x0, 0(x8)
70 csrr x5, mepc
71 addi x5, x5, 4
72 csrw mepc, x5
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi12 /* SCFG DEVALT 0 */
14 alts = <&scfg 0x00 0x0 0>;
17 alts = <&scfg 0x00 0x3 1>;
21 alts = <&scfg 0x00 0x7 1>;
26 alts = <&scfg 0x01 0x0 0>;
29 alts = <&scfg 0x01 0x2 0>;
32 alts = <&scfg 0x01 0x3 0>;
35 alts = <&scfg 0x01 0x4 1>;
38 alts = <&scfg 0x01 0x5 0>;
41 alts = <&scfg 0x01 0x6 0>;
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dcc1352r1_launchxl.overlay9 /* 0x5 is ADC_COMPB_IN_VDDS (power supply measurement) */
10 io-channels = <&adc0 0x5>;
18 #size-cells = <0>;
Dcc1352r_sensortag.overlay9 /* 0x5 is ADC_COMPB_IN_VDDS (power supply measurement) */
10 io-channels = <&adc0 0x5>;
18 #size-cells = <0>;
Dcc26x2r1_launchxl.overlay9 /* 0x5 is ADC_COMPB_IN_VDDS (power supply measurement) */
10 io-channels = <&adc0 0x5>;
18 #size-cells = <0>;
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-alts-map.dtsi15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x02 0x7 0>;
30 alts = <&scfg 0x05 0x1 0>;
33 alts = <&scfg 0x05 0x7 0>;
38 alts = <&scfg 0x0E 0x6 0>;
41 alts = <&scfg 0x0E 0x7 0>;
46 alts = <&scfg 0x0F 0x5 0>;
49 alts = <&scfg 0x0F 0x6 0>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-alts-map.dtsi15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x05 0x1 0>;
30 alts = <&scfg 0x0E 0x6 0>;
33 alts = <&scfg 0x0E 0x7 0>;
38 alts = <&scfg 0x0F 0x5 0>;
41 alts = <&scfg 0x0F 0x6 0>;
46 alts = <&scfg 0x10 0x4 0>;
49 alts = <&scfg 0x10 0x5 0>;
[all …]
/Zephyr-latest/samples/boards/bbc/microbit/display/
DREADME.rst4 Use the 5x5 LED matrix display on the BBC micro:bit board.
8 A simple example that demonstrates how to use the 5x5 LED matrix display
26 The sample app displays a countdown of the characters 9-0, iterates
/Zephyr-latest/arch/arm64/core/
Dreset.S91 msr SPSel, #0
122 msr DAIFSet, #0xf
160 mov x5, #0
161 2: ldrb w3, [x4, x5]
165 add x5, x5, #1
166 cmp x5, #CONFIG_MP_MAX_NUM_CPUS
199 * Initialize the interrupt stack with 0xaa so stack utilization
207 mov x10, 0xaaaaaaaaaaaaaaaa
Dcoredump.c26 uint64_t x5; member
68 (void)memset(&arch_blk, 0, sizeof(arch_blk)); in arch_coredump_info_dump()
79 arch_blk.r.x5 = esf->x5; in arch_coredump_info_dump()
Duserspace.S29 mov x0, #0
30 mov x4, #0
40 cbz x5, strlen_done
47 mov x0, #0
75 tbnz x4, #0, abv_fail
81 mov x0, #0
98 ldp x4, x5, [sp, ___esf_t_x4_x5_OFFSET]
/Zephyr-latest/tests/drivers/build_all/sensor/
Di3c.dtsi15 reg = <0x1 0x00000803 0xE0000001>;
16 assigned-address = <0x1>;
17 drdy-gpios = <&test_gpio 0 0>;
22 reg = <0x2 0x00000803 0xE0000002>;
23 assigned-address = <0x2>;
24 drdy-gpios = <&test_gpio 0 0>;
29 reg = <0x3 0x00000803 0xE0000003>;
30 assigned-address = <0x3>;
31 drdy-gpios = <&test_gpio 0 0>;
36 reg = <0x3 0x00000803 0xE0000004>;
[all …]
/Zephyr-latest/dts/bindings/dma/
Dandestech,atcdmac300.yaml35 -bit 0-1 : Direction (see dma.h)
36 0x0: MEM to MEM
37 0x1: MEM to PERIPH
38 0x2: PERIPH to MEM
39 0x3: reserved for PERIPH to PERIPH
41 0x0: no address increment between transfers
42 0x1: increment address between transfers
44 0x0: no address increment between transfers
45 0x1: increment address between transfers
47 0x0: Byte (8 bits)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Ddma_smartbond.h17 #define DMA_SMARTBOND_TRIG_MUX_SPI 0x0
18 #define DMA_SMARTBOND_TRIG_MUX_SPI2 0x1
19 #define DMA_SMARTBOND_TRIG_MUX_UART 0x2
20 #define DMA_SMARTBOND_TRIG_MUX_UART2 0x3
21 #define DMA_SMARTBOND_TRIG_MUX_I2C 0x4
22 #define DMA_SMARTBOND_TRIG_MUX_I2C2 0x5
23 #define DMA_SMARTBOND_TRIG_MUX_USB 0x6
24 #define DMA_SMARTBOND_TRIG_MUX_UART3 0x7
25 #define DMA_SMARTBOND_TRIG_MUX_PCM 0x8
26 #define DMA_SMARTBOND_TRIG_MUX_SRC 0x9
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/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_smartbond.h18 DMA_SMARTBOND_TRIG_MUX_SPI = 0x0,
19 DMA_SMARTBOND_TRIG_MUX_SPI2 = 0x1,
20 DMA_SMARTBOND_TRIG_MUX_UART = 0x2,
21 DMA_SMARTBOND_TRIG_MUX_UART2 = 0x3,
22 DMA_SMARTBOND_TRIG_MUX_I2C = 0x4,
23 DMA_SMARTBOND_TRIG_MUX_I2C2 = 0x5,
24 DMA_SMARTBOND_TRIG_MUX_USB = 0x6,
25 DMA_SMARTBOND_TRIG_MUX_UART3 = 0x7,
26 DMA_SMARTBOND_TRIG_MUX_PCM = 0x8,
27 DMA_SMARTBOND_TRIG_MUX_SRC = 0x9,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/adc/
Dmcux-lpadc.h10 #define MCUX_LPADC_CH0A (0x0)
11 #define MCUX_LPADC_CH0B (0x20)
12 #define MCUX_LPADC_CH1A (0x1)
13 #define MCUX_LPADC_CH1B (0x21)
14 #define MCUX_LPADC_CH2A (0x2)
15 #define MCUX_LPADC_CH2B (0x22)
16 #define MCUX_LPADC_CH3A (0x3)
17 #define MCUX_LPADC_CH3B (0x23)
18 #define MCUX_LPADC_CH4A (0x4)
19 #define MCUX_LPADC_CH4B (0x24)
[all …]

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