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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-alts-map.dtsi15 /* SCFG DEVALT 0 */
17 alts = <&scfg 0x00 0x4 0>;
20 alts = <&scfg 0x00 0x6 0>;
25 alts = <&scfg 0x02 0x7 0>;
30 alts = <&scfg 0x05 0x1 0>;
33 alts = <&scfg 0x05 0x7 0>;
38 alts = <&scfg 0x0E 0x6 0>;
41 alts = <&scfg 0x0E 0x7 0>;
46 alts = <&scfg 0x0F 0x5 0>;
49 alts = <&scfg 0x0F 0x6 0>;
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc1200_rf.h32 0x6F, /* SYNC3 */
33 0x4E,
34 0x90,
35 0x4E,
36 0xE5,
37 0x23,
38 0x47,
39 0x0B,
40 0x56,
41 0x19, /* 0x14 */
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec5.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
27 reg = <0x4000fc00 0x200>;
31 reg = <0x40080100 0x100 0x4000a400 0x100>;
33 interrupts = <174 0>;
37 reg = <0x4000e000 0x400>;
42 ranges = <0x0 0x4000e000 0x400>;
44 girq8: girq8@0 {
45 reg = <0x0 0x14>;
[all …]
Dmec172x_common.dtsi8 reg = <0x4000fc00 0x200>;
12 reg = <0x40080100 0x100 0x4000a400 0x100>;
14 interrupts = <174 0>;
29 reg = <0x4000e000 0x400>;
31 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>;
35 ranges = <0x0 0x4000e000 0x400>;
37 girq8: girq8@0 {
39 reg = <0x0 0x14>;
40 interrupts = <0 0>;
41 girq-id = <0>;
[all …]
/Zephyr-latest/boards/beagle/beaglebone_ai64/
Dbeaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi13 /* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */
14 pinmux = <K3_PINMUX(0x1c, PIN_OUTPUT, MUX_MODE_14)>;
18 /* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
19 pinmux = <K3_PINMUX(0x14, PIN_INPUT, MUX_MODE_14)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dmcux_lpc_syscon_clock.h19 #define MCUX_CTIMER0_CLK 0
25 #define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00)
26 #define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01)
27 #define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02)
28 #define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03)
29 #define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04)
30 #define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05)
31 #define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06)
32 #define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07)
33 #define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dst,lsm6dso16is-common.yaml12 lsm6dso16is: lsm6dso16is@0 {
49 default: 0
53 - 0 # LSM6DSO16IS_DT_FS_2G (0.061 mg/LSB)
58 enum: [0, 1, 2, 3]
62 default: 0x0
69 - 0x00 # LSM6DSO16IS_DT_ODR_OFF
70 - 0x01 # LSM6DSO16IS_DT_ODR_12Hz5_HP
71 - 0x02 # LSM6DSO16IS_DT_ODR_26H_HP
72 - 0x03 # LSM6DSO16IS_DT_ODR_52Hz_HP
73 - 0x04 # LSM6DSO16IS_DT_ODR_104Hz_HP
[all …]
/Zephyr-latest/arch/sparc/core/
Dstack_offsets.h16 #define STACK_FRAME_L0_OFFSET 0x00
17 #define STACK_FRAME_L1_OFFSET 0x04
18 #define STACK_FRAME_L2_OFFSET 0x08
19 #define STACK_FRAME_L3_OFFSET 0x0c
20 #define STACK_FRAME_L4_OFFSET 0x10
21 #define STACK_FRAME_L5_OFFSET 0x14
22 #define STACK_FRAME_L6_OFFSET 0x18
23 #define STACK_FRAME_L7_OFFSET 0x1c
24 #define STACK_FRAME_I0_OFFSET 0x20
25 #define STACK_FRAME_I1_OFFSET 0x24
[all …]
/Zephyr-latest/samples/modules/tflite-micro/hello_world/src/
Dmodel.cpp31 0x1c, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x14, 0x00, 0x20, 0x00,
32 0x1c, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x00, 0x00,
33 0x08, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00,
34 0x98, 0x00, 0x00, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x1c, 0x03, 0x00, 0x00,
35 0x2c, 0x03, 0x00, 0x00, 0x30, 0x09, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
36 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x60, 0xf7, 0xff, 0xff,
37 0x10, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00,
38 0x44, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76,
39 0x65, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76,
40 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x00,
[all …]
/Zephyr-latest/samples/modules/tflite-micro/tflm_ethosu/src/models/keyword_spotting_cnn_small_int8/
Dinput.h8 0x2c, 0x8a, 0xff, 0x0c, 0xaf, 0x2a, 0x44, 0x17, 0xf5, 0x26, 0x96, 0x37, 0x40, 0x4c, 0xa1,
9 0x58, 0xc3, 0x33, 0xce, 0x1a, 0x7b, 0xd2, 0x22, 0x5b, 0x43, 0xf6, 0xfd, 0x0b, 0xe7, 0xfd,
10 0x65, 0x58, 0x89, 0x24, 0xf4, 0xec, 0x53, 0x5e, 0x21, 0x1f, 0x95, 0xd1, 0xd9, 0x25, 0x72,
11 0x56, 0xe6, 0xe2, 0xa4, 0x37, 0x85, 0xf0, 0xd7, 0xba, 0xab, 0xcc, 0xc6, 0xbc, 0xcb, 0x64,
12 0x58, 0x3d, 0x04, 0x8e, 0xd8, 0x1a, 0x32, 0x76, 0x0c, 0x4d, 0x4c, 0xc5, 0xba, 0xb9, 0xa9,
13 0xe2, 0x41, 0xc2, 0xc8, 0xfa, 0x66, 0xfd, 0x2e, 0x4a, 0xa7, 0xca, 0x6a, 0x4f, 0xd7, 0x28,
14 0xe5, 0x07, 0x2e, 0x48, 0x5f, 0xfa, 0xd8, 0xde, 0xeb, 0x11, 0xd1, 0x0b, 0x0d, 0xe4, 0x25,
15 0x66, 0x73, 0x6c, 0x99, 0xc2, 0x89, 0x56, 0xcd, 0xeb, 0xaf, 0x92, 0xc8, 0x18, 0xdf, 0xd6,
16 0x89, 0x9b, 0xce, 0x96, 0x14, 0x17, 0x6e, 0x25, 0xf3, 0x88, 0xad, 0x85, 0x50, 0x93, 0xc5,
17 0xde, 0x73, 0x12, 0xa6, 0x55, 0x45, 0x9e, 0x88, 0x75, 0x7e, 0xc7, 0xb5, 0x47, 0xcf, 0x87,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32l1_reset.h13 #define STM32_RESET_BUS_AHB1 0x10
14 #define STM32_RESET_BUS_APB1 0x18
15 #define STM32_RESET_BUS_APB2 0x14
Dstm32f2_4_7_reset.h13 #define STM32_RESET_BUS_AHB1 0x10
14 #define STM32_RESET_BUS_AHB2 0x14
15 #define STM32_RESET_BUS_AHB3 0x18
16 #define STM32_RESET_BUS_APB1 0x20
17 #define STM32_RESET_BUS_APB2 0x24
/Zephyr-latest/tests/lib/cmsis_dsp/matrix/src/
Dbinary_q7.pat2 0x29, 0xFF, 0x63, 0x16, 0x2D, 0xFC, 0xDA, 0x05,
3 0xDE, 0x22, 0xDE, 0x06, 0x21, 0x11, 0x01, 0xC9,
4 0x29, 0xFC, 0x4B, 0x17, 0xD1, 0x48, 0xF8, 0x08,
5 0xA8, 0xFC, 0x17, 0xFF, 0x12, 0x15, 0x40, 0xC8,
6 0xD0, 0xA0, 0xE2, 0xEB, 0x0D, 0xF9, 0xD1, 0xD8,
7 0xF5, 0x2C, 0x08, 0xF3, 0xD9, 0x03, 0xD7, 0xE8,
8 0xFE, 0x2C, 0x0C, 0xF5, 0x2C, 0x14, 0xFC, 0xFB,
9 0xEE, 0x0C, 0xFC, 0x15, 0xD9, 0xE6, 0xFA, 0xF5,
10 0x10, 0x11, 0x0F, 0x13, 0xC9, 0xEF, 0x1C, 0xCB,
11 0xD5, 0xCA, 0x18, 0xF9, 0xFC, 0x03, 0xBA, 0x46,
[all …]
/Zephyr-latest/tests/subsys/dsp/basicmath/src/
Dq7.pat2 0x52, 0x01, 0x47, 0x20, 0xA5, 0xFD, 0xFC, 0x44,
3 0xF5, 0xCB, 0x2A, 0xE7, 0x1E, 0x28, 0xFF, 0xEF,
4 0x3E, 0x2C, 0x05, 0x32, 0xAE, 0x09, 0xBE, 0xF5,
5 0x24, 0xFA, 0xDE, 0xD6, 0xF4, 0xE7, 0x0D, 0xD7,
6 0x10, 0x19, 0x0C, 0xC8, 0xBB, 0x1E, 0x05, 0xAA,
7 0x44, 0x60, 0x2D, 0x21, 0x1C, 0xF0, 0x2E, 0x25,
8 0xF4, 0xF1, 0xC7, 0x19, 0x26, 0xBB, 0xD0, 0x08,
9 0x46, 0xF9, 0xEF, 0x7E, 0x19, 0x1E, 0x1B, 0x0A,
10 0x1F, 0x22, 0x12, 0x10, 0x13, 0x05, 0x41, 0x0F,
11 0x3B, 0xF6, 0xF9, 0x45, 0xE5, 0xE4, 0x14, 0xCD,
[all …]
/Zephyr-latest/drivers/fuel_gauge/max17048/
Dmax17048.h13 #define REGISTER_VCELL 0x02
14 #define REGISTER_SOC 0x04
15 #define REGISTER_MODE 0x06
16 #define REGISTER_VERSION 0x08
17 #define REGISTER_HIBRT 0x0A
18 #define REGISTER_CONFIG 0x0C
19 #define REGISTER_VALRT 0x14
20 #define REGISTER_CRATE 0x16
21 #define REGISTER_VRESET 0x18
22 #define REGISTER_CHIP_ID 0x19
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_xlnx_ipi.h11 #define IPI_CH0_BIT 0
24 #define IPI_TRIG 0x00
25 #define IPI_OBS 0x04
26 #define IPI_ISR 0x10
27 #define IPI_IMR 0x14
28 #define IPI_IER 0x18
29 #define IPI_IDR 0x1C
/Zephyr-latest/arch/arm64/core/
Dcoredump.c35 uint64_t x14; member
68 (void)memset(&arch_blk, 0, sizeof(arch_blk)); in arch_coredump_info_dump()
88 arch_blk.r.x14 = esf->x14; in arch_coredump_info_dump()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h13 #define CLKMGR_OFFSET 0xffd10000
15 #define CLKMGR_CTRL 0x0
16 #define CLKMGR_STAT 0x4
17 #define CLKMGR_INTRCLR 0x14
20 #define CLKMGR_MAINPLL 0xffd10024
21 #define CLKMGR_MAINPLL_EN 0x0
22 #define CLKMGR_MAINPLL_BYPASS 0xc
23 #define CLKMGR_MAINPLL_MPUCLK 0x18
24 #define CLKMGR_MAINPLL_NOCCLK 0x1c
25 #define CLKMGR_MAINPLL_NOCDIV 0x20
[all …]
/Zephyr-latest/dts/bindings/firmware/
Darm,scmi-clock.yaml16 const: [0x14]
/Zephyr-latest/samples/net/mqtt_publisher/src/
Dtest_certs.h31 0x30, 0x82, 0x02, 0xfb, 0x30, 0x82, 0x01, 0xe3,
32 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x09, 0x00,
33 0xee, 0x10, 0x1f, 0xc1, 0xf2, 0x30, 0xe9, 0x11,
34 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86,
35 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30,
36 0x14, 0x31, 0x12, 0x30, 0x10, 0x06, 0x03, 0x55,
37 0x04, 0x03, 0x0c, 0x09, 0x6c, 0x6f, 0x63, 0x61,
38 0x6c, 0x68, 0x6f, 0x73, 0x74, 0x30, 0x1e, 0x17,
39 0x0d, 0x31, 0x37, 0x30, 0x36, 0x32, 0x36, 0x31,
40 0x30, 0x35, 0x36, 0x31, 0x30, 0x5a, 0x17, 0x0d,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dso16is.h10 #define LSM6DSO16IS_DT_FS_2G 0
16 #define LSM6DSO16IS_DT_FS_250DPS 0x0
17 #define LSM6DSO16IS_DT_FS_500DPS 0x1
18 #define LSM6DSO16IS_DT_FS_1000DPS 0x2
19 #define LSM6DSO16IS_DT_FS_2000DPS 0x3
20 #define LSM6DSO16IS_DT_FS_125DPS 0x10
23 #define LSM6DSO16IS_DT_ODR_OFF 0x0
24 #define LSM6DSO16IS_DT_ODR_12Hz5_HP 0x1
25 #define LSM6DSO16IS_DT_ODR_26H_HP 0x2
26 #define LSM6DSO16IS_DT_ODR_52Hz_HP 0x3
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4m/boards/
Dmimxrt595_evk_mimxrt595s_cm33.overlay18 alt-addr = <0x14>;
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/boards/
Dmimxrt595_evk_mimxrt595s_cm33.overlay18 alt-addr = <0x14>;
/Zephyr-latest/tests/subsys/settings/file/src/
Dsettings_test_compress_file.c14 "\x0d\x00myfoo/mybar=\x14"\
17 #define EXP_STR_CONTENT_2 "\x0d\x00myfoo/mybar=\x14"\
31 zassert_true(rc == 0 || rc == -EEXIST, "can't create directory"); in ZTEST()
35 cf.cf_lines = 0; /* required as not start with load settings */ in ZTEST()
38 zassert_true(rc == 0, "can't register FS as configuration source"); in ZTEST()
42 zassert_true(rc == 0, in ZTEST()
48 for (int i = 0; i < 21; i++) { in ZTEST()
51 zassert_true(rc == 0, "fs write error"); in ZTEST()
53 val8 = 0xff; in ZTEST()
60 zassert_true(rc == 0, "fs write error"); in ZTEST()
[all …]
/Zephyr-latest/include/zephyr/usb/class/
Dusb_hub.h16 #define USB_HCFS_C_HUB_LOCAL_POWER 0x00
17 #define USB_HCFS_C_HUB_OVER_CURRENT 0x01
18 #define USB_HCFS_PORT_CONNECTION 0x00
19 #define USB_HCFS_PORT_ENABLE 0x01
20 #define USB_HCFS_PORT_SUSPEND 0x02
21 #define USB_HCFS_PORT_OVER_CURRENT 0x03
22 #define USB_HCFS_PORT_RESET 0x04
23 #define USB_HCFS_PORT_POWER 0x08
24 #define USB_HCFS_PORT_LOW_SPEED 0x09
25 #define USB_HCFS_C_PORT_CONNECTION 0x10
[all …]

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