Lines Matching +full:0 +full:x14
16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
27 reg = <0x4000fc00 0x200>;
31 reg = <0x40080100 0x100 0x4000a400 0x100>;
33 interrupts = <174 0>;
37 reg = <0x4000e000 0x400>;
42 ranges = <0x0 0x4000e000 0x400>;
44 girq8: girq8@0 {
45 reg = <0x0 0x14>;
46 interrupts = <0 1>;
50 reg = <0x14 0x14>;
55 reg = <0x28 0x14>;
60 reg = <0x3c 0x14>;
65 reg = <0x50 0x14>;
70 reg = <0x64 0x14>;
75 reg = <0x78 0x14>;
80 reg = <0x8c 0x14>;
85 reg = <0xa0 0x14>;
90 reg = <0xb4 0x14>;
95 reg = <0xc8 0x14>;
100 reg = <0xdc 0x14>;
105 reg = <0xf0 0x14>;
110 reg = <0x104 0x14>;
115 reg = <0x118 0x14>;
116 interrupts = <255 0>;
120 reg = <0x12c 0x14>;
125 reg = <0x140 0x14>;
130 reg = <0x154 0x14>;
135 reg = <0x168 0x14>;
144 reg = <0x40081000 0x1000>;
148 reg = < 0x40081000 0x80 0x40081300 0x04
149 0x40081380 0x04 0x400813fc 0x04>;
156 reg = < 0x40081080 0x80 0x40081304 0x04
157 0x40081384 0x04 0x400813f8 0x4>;
164 reg = < 0x40081100 0x80 0x40081308 0x04
165 0x40081388 0x04 0x400813f4 0x04>;
172 reg = < 0x40081180 0x80 0x4008130c 0x04
173 0x4008138c 0x04 0x400813f0 0x04>;
175 interrupts = <0 2>;
180 reg = < 0x40081200 0x80 0x40081310 0x04
181 0x40081390 0x04 0x400813ec 0x04>;
188 reg = < 0x40081280 0x80 0x40081314 0x04
189 0x40081394 0x04 0x400813e8 0x04>;
196 reg = <0x400f2400 0x400>;
201 reg = <0x400f2800 0x400>;
206 reg = <0x40000400 0x400>;
207 interrupts = <171 0>;
211 reg = <0x40007400 0x10>;
212 interrupts = <111 0>;
214 max-value = <0xffffffff>;
218 reg = <0x40000c00 0x20>;
219 interrupts = <136 0>;
221 prescaler = <0>;
222 max-value = <0xffff>;
226 reg = <0x40000c20 0x20>;
227 interrupts = <137 0>;
229 prescaler = <0>;
230 max-value = <0xffff>;
234 reg = <0x40000c40 0x20>;
235 interrupts = <138 0>;
237 prescaler = <0>;
238 max-value = <0xffff>;
242 reg = <0x40000c60 0x20>;
243 interrupts = <139 0>;
245 prescaler = <0>;
246 max-value = <0xffff>;
250 reg = <0x40000c80 0x20>;
251 interrupts = <140 0>;
253 prescaler = <0>;
254 max-value = <0xffffffff>;
258 reg = <0x40000ca0 0x20>;
259 interrupts = <141 0>;
261 prescaler = <0>;
262 max-value = <0xffffffff>;
266 reg = <0x40000d00 0x20>;
267 interrupts = <142 0>;
271 reg = <0x40000d20 0x20>;
272 interrupts = <143 0>;
276 reg = <0x40000d40 0x20>;
277 interrupts = <144 0>;
281 reg = <0x40000d60 0x20>;
282 interrupts = <145 0>;
286 reg = <0x40001000 0x40>;
287 interrupts = <146 0>, <147 0>, <148 0>, <149 0>,
288 <150 0>, <151 0>, <152 0>, <153 0>,
289 <154 0>;
293 reg = <0x40009800 0x20>;
294 interrupts = <112 0>;
298 reg = <0x40009820 0x20>;
299 interrupts = <113 0>;
303 reg = <0x4000ac80 0x80>;
304 interrupts = <114 0>, <115 0>, <116 0>,
305 <117 0>, <118 0>;
309 reg = <0x400f5000 0x100>;
314 reg = <0x4000a800 0x100>;
319 reg = <0x4000ae00 0x40>;
320 interrupts = <121 0>, <122 0>, <123 0>,
321 <124 0>, <125 0>;
325 reg = <0x40004000 0x80>;
329 #size-cells = <0>;
333 reg = <0x40004400 0x80>;
337 #size-cells = <0>;
341 reg = <0x40004800 0x80>;
345 #size-cells = <0>;
349 reg = <0x40004C00 0x80>;
353 #size-cells = <0>;
357 reg = <0x40005000 0x80>;
361 #size-cells = <0>;
365 reg = <0x40009000 0x40>;
368 #size-cells = <0>;
372 reg = <0x40005800 0x10>;
377 reg = <0x40005810 0x10>;
382 reg = <0x40005820 0x10>;
387 reg = <0x40005830 0x10>;
392 reg = <0x40005840 0x10>;
397 reg = <0x40005850 0x10>;
402 reg = <0x40005860 0x10>;
407 reg = <0x40005870 0x10>;
412 reg = <0x40005880 0x10>;
417 reg = <0x40006000 0x10>;
420 #size-cells = <0>;
424 reg = <0x40006010 0x10>;
427 #size-cells = <0>;
431 reg = <0x40006020 0x10>;
434 #size-cells = <0>;
438 reg = <0x40006030 0x10>;
441 #size-cells = <0>;
445 reg = <0x4000a000 0x80>;
450 reg = <0x4000a080 0x80>;
455 reg = <0x40007c00 0x90>;
456 interrupts = <78 0>, <79 0>;
463 reg = <0x40006400 0x80>;
466 #size-cells = <0>;
470 reg = <0x40070000 0x400>;
474 #size-cells = <0>;
478 reg = <0x40003400 0x20>;
479 interrupts = <87 0>;
483 reg = <0x40001400 0x80>;
484 interrupts = <80 0>;
488 reg = <0x40001480 0x80>;
489 interrupts = <81 0>;
493 reg = <0x40001500 0x80>;
494 interrupts = <82 0>;
498 reg = <0x4000b800 0x100>;
499 interrupts = <83 0>;
503 reg = <0x4000b900 0x100>;
504 interrupts = <84 0>;
508 reg = <0x4000ba00 0x100>;
509 interrupts = <85 0>;
513 reg = <0x4000bb00 0x100>;
514 interrupts = <86 0>;
518 reg = <0x4000cd00 0x20>;
519 interrupts = <96 0>, <97 0>;
523 reg = <0x40008c00 0x10>;
527 reg = <0x400fff00 0x40>;
533 reg = < 0x400f3400 0x400
534 0x400f3800 0x400
535 0x400f9c00 0x400>;
551 reg = <0x400f0000 0x200>;
556 reg = <0x400f0400 0x400>, <0x400f2000 0x400>;
562 reg = <0x400f0800 0x400>;
568 reg = <0x400f0c00 0x400>;
574 reg = <0x400f1000 0x400>;
580 reg = <0x400f1400 0x400>;
586 reg = <0x400f1800 0x400>;
592 reg = <0x400f1c00 0x400>;
598 reg = <0x400f3c00 0x200>;
603 reg = <0x400f4000 0x400>;
608 reg = <0x400f4400 0x400>;
613 reg = <0x400f4800 0x400>;
622 reg = <0x400f8000 0x400>;
623 interrupts = <62 0>;
633 reg = <0x40008000 0x400>, <0x40070000 0x400>, <0x40071000 0x400>;