Lines Matching +full:0 +full:x14
8 reg = <0x4000fc00 0x200>;
12 reg = <0x40080100 0x100 0x4000a400 0x100>;
14 interrupts = <174 0>;
29 reg = <0x4000e000 0x400>;
31 clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>;
35 ranges = <0x0 0x4000e000 0x400>;
37 girq8: girq8@0 {
39 reg = <0x0 0x14>;
40 interrupts = <0 0>;
41 girq-id = <0>;
42 sources = <0 1 2 3 4 5 6 7
50 reg = <0x14 0x14>;
51 interrupts = <1 0>;
53 sources = <0 1 2 3 4 5 6 7
61 reg = <0x28 0x14>;
62 interrupts = <2 0>;
64 sources = <0 1 2 3 4 5 6 7
72 reg = <0x3c 0x14>;
73 interrupts = <3 0>;
75 sources = <0 1 2 3 4 5 6 7
83 reg = <0x50 0x14>;
84 interrupts = <4 0>;
86 sources = <0 1 2 3 4 5 6 7
94 reg = <0x64 0x14>;
95 interrupts = <5 0>;
97 sources = <0 1 2 3 4>;
102 reg = <0x78 0x14>;
103 interrupts = <6 0>;
105 sources = <0 1 2 3 4 5 6 7
111 reg = <0x8c 0x14>;
112 interrupts = <7 0>;
114 sources = <0 1 2 3 4 5 6 7
121 reg = <0xa0 0x14>;
122 interrupts = <8 0>;
124 sources = <0 2 3>;
129 reg = <0xb4 0x14>;
130 interrupts = <9 0>;
132 sources = <0 1 2 3 4 8 9 10 11 12 13 14 15
138 reg = <0xc8 0x14>;
139 interrupts = <10 0>;
141 sources = <0 1 2 3 4 5 6 7
148 reg = <0xdc 0x14>;
149 interrupts = <11 0>;
151 sources = <0 1 2 3 4 5 6 7 8 9 10>;
156 reg = <0xf0 0x14>;
157 interrupts = <12 0>;
164 reg = <0x104 0x14>;
165 interrupts = <13 0>;
173 reg = <0x118 0x14>;
174 interrupts = <255 0>;
176 sources = <0 1 2 3 4 5 9 15>;
181 reg = <0x12c 0x14>;
182 interrupts = <14 0>;
184 sources = <0 1 2 3 4 5 6 7 8 9 10 16 17>;
189 reg = <0x140 0x14>;
190 interrupts = <15 0>;
192 sources = <0 1 2 3 4 5 6 7 8 9 10 11
199 reg = <0x154 0x14>;
200 interrupts = <16 0>;
202 sources = <0 1 2 3 4 5 6 7 8 9 10 11
208 reg = <0x168 0x14>;
209 interrupts = <17 0>;
211 sources = <0 1 2 3 4 5 6 12 13>;
219 reg = <0x40081000 0x1000>;
223 reg = < 0x40081000 0x80 0x40081300 0x04
224 0x40081380 0x04 0x400813fc 0x04>;
227 port-id = <0>;
233 reg = < 0x40081080 0x80 0x40081304 0x04
234 0x40081384 0x04 0x400813f8 0x4>;
243 reg = < 0x40081100 0x80 0x40081308 0x04
244 0x40081388 0x04 0x400813f4 0x04>;
253 reg = < 0x40081180 0x80 0x4008130c 0x04
254 0x4008138c 0x04 0x400813f0 0x04>;
256 interrupts = <0 2>;
263 reg = < 0x40081200 0x80 0x40081310 0x04
264 0x40081390 0x04 0x400813ec 0x04>;
273 reg = < 0x40081280 0x80 0x40081314 0x04
274 0x40081394 0x04 0x400813e8 0x04>;
284 reg = <0x40000400 0x400>;
285 interrupts = <171 0>;
291 reg = <0x40007400 0x10>;
292 interrupts = <111 0>;
298 reg = <0x40000c00 0x20>;
299 interrupts = <136 0>;
300 girqs = <23 0>;
302 max-value = <0xFFFF>;
303 prescaler = <0>;
309 reg = <0x40000c20 0x20>;
310 interrupts = <137 0>;
313 max-value = <0xFFFF>;
314 prescaler = <0>;
320 reg = <0x40000c40 0x20>;
321 interrupts = <138 0>;
324 max-value = <0xFFFF>;
325 prescaler = <0>;
331 reg = <0x40000c60 0x20>;
332 interrupts = <139 0>;
335 max-value = <0xFFFF>;
336 prescaler = <0>;
347 reg = <0x40000c80 0x20>;
348 interrupts = <140 0>;
351 max-value = <0xFFFFFFFF>;
352 prescaler = <0>;
358 reg = <0x40000ca0 0x20>;
359 interrupts = <141 0>;
362 max-value = <0xFFFFFFFF>;
363 prescaler = <0>;
367 reg = <0x40000d00 0x20>;
368 interrupts = <142 0>;
374 reg = <0x40000d20 0x20>;
375 interrupts = <143 0>;
381 reg = <0x40000d40 0x20>;
382 interrupts = <144 0>;
388 reg = <0x40000d60 0x20>;
389 interrupts = <145 0>;
395 reg = <0x40001000 0x40>;
396 interrupts = <146 0>, <147 0>, <148 0>, <149 0>,
397 <150 0>, <151 0>, <152 0>, <153 0>,
398 <154 0>;
405 reg = <0x40009800 0x20>;
406 interrupts = <112 0>;
410 reg = <0x40009820 0x20>;
411 interrupts = <113 0>;
415 reg = <0x4000ac80 0x80>;
416 interrupts = <114 0>, <115 0>, <116 0>,
417 <117 0>, <118 0>;
423 reg = <0x4000a800 0x100>;
427 reg = <0x4000ae00 0x40>;
428 interrupts = <121 0>, <122 0>, <123 0>,
429 <124 0>, <125 0>;
435 reg = <0x40002400 0xc00>;
440 girqs = < MCHP_XEC_ECIA(14, 0, 6, 24)
464 reg = <0x40004000 0x80>;
467 girqs = <13 0>;
470 #size-cells = <0>;
475 reg = <0x40004400 0x80>;
481 #size-cells = <0>;
486 reg = <0x40004800 0x80>;
492 #size-cells = <0>;
497 reg = <0x40004C00 0x80>;
503 #size-cells = <0>;
508 reg = <0x40005000 0x80>;
514 #size-cells = <0>;
519 reg = <0x40009000 0x40>;
524 #size-cells = <0>;
529 reg = <0x40005800 0x20>;
536 reg = <0x40005810 0x20>;
543 reg = <0x40005820 0x20>;
550 reg = <0x40005830 0x20>;
557 reg = <0x40005840 0x20>;
564 reg = <0x40005850 0x20>;
571 reg = <0x40005860 0x20>;
578 reg = <0x40005870 0x20>;
585 reg = <0x40005880 0x20>;
592 reg = <0x40006000 0x10>;
597 #size-cells = <0>;
602 reg = <0x40006010 0x10>;
607 #size-cells = <0>;
612 reg = <0x40006020 0x10>;
617 #size-cells = <0>;
622 reg = <0x40006030 0x10>;
627 #size-cells = <0>;
631 reg = <0x4000a000 0x80>;
638 reg = <0x4000a080 0x80>;
646 reg = <0x40007c00 0x90>;
647 interrupts = <78 0>, <79 0>;
657 reg = <0x40009c00 0x18>;
658 interrupts = <135 0>;
663 #size-cells = <0>;
667 reg = <0x40006400 0x80>;
669 girqs = <17 0>;
672 #size-cells = <0>;
675 reg = <0x40070000 0x400>;
681 chip-select = <0>;
683 #size-cells = <0>;
687 reg = <0x40009400 0x80>;
694 reg = <0x40009480 0x80>;
701 reg = <0x40003400 0x20>;
702 interrupts = <87 0>;
708 reg = <0x40001400 0x80>;
709 interrupts = <80 0>;
715 reg = <0x40001480 0x80>;
716 interrupts = <81 0>;
722 reg = <0x40001500 0x80>;
723 interrupts = <82 0>;
729 reg = <0x40007000 0x100>;
730 interrupts = <90 0>;
731 girqs = <18 0>;
736 reg = <0x4000b800 0x100>;
737 interrupts = <83 0>;
743 reg = <0x4000b900 0x100>;
744 interrupts = <84 0>;
750 reg = <0x4000ba00 0x100>;
751 interrupts = <85 0>;
757 reg = <0x4000bb00 0x100>;
758 interrupts = <86 0>;
764 reg = <0x4000cd00 0x20>;
765 interrupts = <96 0>, <97 0>;
771 reg = <0x40008c00 0x10>;
776 reg = <0x400fff00 0x40>;
782 reg = <0x400f2400 0x400>;
786 girqs = <15 0>;
793 reg = <0x400f2800 0x400>;
809 reg = < 0x400f3400 0x400
810 0x400f3800 0x400
811 0x400f9c00 0x400>;
818 girqs = < MCHP_XEC_ECIA(19, 0, 11, 103)
832 reg = <0x40008000 0x400>, <0x40070000 0x400>,
833 <0x40071000 0x400>;
845 reg = <0x400f0000 0x200>;
849 ldn = <0>;
854 reg = <0x400f0400 0x400>;
864 reg = <0x400f0800 0x400>;
874 reg = <0x400f0c00 0x400>;
884 reg = <0x400f1000 0x400>;
894 reg = <0x400f1400 0x400>;
904 reg = <0x400f1800 0x400>;
914 reg = <0x400f1c00 0x400>;
925 reg = <0x400f2000 0x400>;
931 reg = <0x400f4000 0x400>;
939 reg = <0x400f4400 0x400>;
947 reg = <0x400f4800 0x400>;
955 reg = <0x400f5000 0x100>;
963 /* Capture writes to host I/O 0x80 - 0x83 */
966 reg = <0x400f8000 0x400>;
967 interrupts = <62 0>;
973 /* Capture writes to an 8-bit I/O and map to one of 0x80 to 0x83 */
976 reg = <0x400f8400 0x400>;
978 host-io = <0x90>;
979 /* map 0x90 to 0x80 */
980 host-io-addr-mask = <0x01>;
987 reg = <0x40100000 0x1000>;
997 reg = <0x1f000 0x1000>;