| /Zephyr-latest/scripts/dts/python-devicetree/tests/ |
| D | test.dts | 4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
23 interrupts = <1 2 3 4 5 6>;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat3/xmc/ |
| D | xmc4500_F100x1024-intc.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
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| D | xmc4700_F144x2048-intc.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
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| D | xmc4500_F100x1024-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
10 /omit-if-no-ref/ uart_tx_p0_1_u1c1: uart_tx_p0_1_u1c1 {
11 pinmux = <XMC4XXX_PINMUX_SET(0, 1, 2)>;
13 /omit-if-no-ref/ uart_tx_p0_5_u1c0: uart_tx_p0_5_u1c0 {
14 pinmux = <XMC4XXX_PINMUX_SET(0, 5, 2)>;
16 /omit-if-no-ref/ uart_tx_p1_5_u0c0: uart_tx_p1_5_u0c0 {
17 pinmux = <XMC4XXX_PINMUX_SET(1, 5, 2)>;
19 /omit-if-no-ref/ uart_tx_p1_7_u0c0: uart_tx_p1_7_u0c0 {
20 pinmux = <XMC4XXX_PINMUX_SET(1, 7, 2)>;
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc11u6x.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
6 #include <arm/armv6-m.dtsi>
7 #include <zephyr/dt-bindings/clock/lpc11u6x_clock.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
16 cpu0: cpu@0 {
17 compatible = "arm,cortex-m0+";
18 reg = <0>;
23 compatible = "mmio-sram";
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| /Zephyr-latest/drivers/video/ |
| D | mt9m114.c | 5 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/video-controls.h>
20 #define MT9M114_CHIP_ID_VAL 0x2481
23 #define MT9M114_CHIP_ID 0x0000
24 #define MT9M114_COMMAND_REGISTER 0x0080
27 #define MT9M114_RST_AND_MISC_CONTROL 0x001A
30 #define MT9M114_CAM_SENSOR_CFG_Y_ADDR_START 0xC800
31 #define MT9M114_CAM_SENSOR_CFG_X_ADDR_START 0xC802
32 #define MT9M114_CAM_SENSOR_CFG_Y_ADDR_END 0xC804
33 #define MT9M114_CAM_SENSOR_CFG_X_ADDR_END 0xC806
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| /Zephyr-latest/subsys/net/ip/ |
| D | net_tc_mapping.h | 10 * SPDX-License-Identifier: Apache-2.0
19 * according to 802.1Q - table I-2.
23 * 0 (default) BE Best effort
24 * 2 EE Excellent effort
36 #if defined(CONFIG_NET_TC_MAPPING_STRICT) && (NET_TC_COUNT > 0)
39 * implementations that do not support the credit-based shaper transmission
41 * Ref: 802.1Q - chapter 8.6.6 - table 8-4
45 static const uint8_t priority2tc_strict_1[] = {0, 0, 0, 0, 0, 0, 0, 0};
47 #if NET_TC_TX_COUNT == 2 || NET_TC_RX_COUNT == 2
48 static const uint8_t priority2tc_strict_2[] = {0, 0, 0, 0, 1, 1, 1, 1};
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ch32v003-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #define CH32V003_PINMUX_PORT_PA 0
12 #define CH32V003_PINMUX_PORT_PD 2
18 #define CH32V003_PINMUX_SPI1_RM 0
21 #define CH32V003_PINMUX_USART1_RM 2
27 /* Port number with 0-2 */
28 #define CH32V003_PINCTRL_PORT_SHIFT 0
29 /* Pin number 0-15 */
30 #define CH32V003_PINCTRL_PIN_SHIFT 2
31 /* Base remap bit 0-31 */
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| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
24 #define BT_UUID_SERVICE_A BT_UUID_DECLARE_16(0xa00a)
29 #define BT_UUID_VALUE_V1 BT_UUID_DECLARE_16(0xb001)
34 #define BT_UUID_VALUE_V2 BT_UUID_DECLARE_16(0xb002)
39 #define BT_UUID_VALUE_V3 BT_UUID_DECLARE_16(0xb003)
41 static uint8_t value_v1_value = 0x01;
43 '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
47 '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3', '3', '3',
[all …]
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| /Zephyr-latest/boards/shields/st7735r/ |
| D | st7735r_ada_160x128.overlay | 2 * Copyright (c) 2020, Kim Bøndergaard, <kim@fam-boendergaard.dk>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
15 compatible = "zephyr,mipi-dbi-spi";
16 spi-dev = <&arduino_spi>;
17 dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
18 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
19 #address-cells = <1>;
20 #size-cells = <0>;
22 st7735r_st7735r_ada_160x128: st7735r@0 {
[all …]
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| /Zephyr-latest/boards/arm/v2m_musca_b1/ |
| D | pinmux.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #define IOMUX_MAIN_INSEL (0x68 >> 2)
14 #define IOMUX_MAIN_OUTSEL (0x70 >> 2)
15 #define IOMUX_MAIN_OENSEL (0x78 >> 2)
16 #define IOMUX_MAIN_DEFAULT_IN (0x80 >> 2)
17 #define IOMUX_ALTF1_INSEL (0x88 >> 2)
18 #define IOMUX_ALTF1_OUTSEL (0x90 >> 2)
19 #define IOMUX_ALTF1_OENSEL (0x98 >> 2)
20 #define IOMUX_ALTF1_DEFAULT_IN (0xA0 >> 2)
21 #define IOMUX_ALTF2_INSEL (0xA8 >> 2)
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| /Zephyr-latest/boards/arm/v2m_musca_s1/ |
| D | pinmux.c | 2 * Copyright (c) 2019-2020 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
13 #define IOMUX_MAIN_INSEL (0x868 >> 2)
14 #define IOMUX_MAIN_OUTSEL (0x870 >> 2)
15 #define IOMUX_MAIN_OENSEL (0x878 >> 2)
16 #define IOMUX_MAIN_DEFAULT_IN (0x880 >> 2)
17 #define IOMUX_ALTF1_INSEL (0x888 >> 2)
18 #define IOMUX_ALTF1_OUTSEL (0x890 >> 2)
19 #define IOMUX_ALTF1_OENSEL (0x898 >> 2)
20 #define IOMUX_ALTF1_DEFAULT_IN (0x8A0 >> 2)
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
14 wui_io80: wui0-1-0 {
15 miwus = <&miwu0 0 0>; /* GPIO80 */
17 wui_io81: wui0-1-1 {
18 miwus = <&miwu0 0 1>; /* GPIO81 */
20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
[all …]
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| D | npcx-miwus-int-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-int-map {
10 map_miwu0_groups: map-miwu0-groups {
11 compatible = "nuvoton,npcx-miwu-int-map";
14 group_b0: group-b0-map {
16 irq-prio = <2>;
17 group-mask = <0x02>;
19 group_c0: group-c0-map {
21 irq-prio = <2>;
22 group-mask = <0x04>;
[all …]
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_em.props | 3 arcver=0x3
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
8 nsim_isa_big_endian=0
12 nsim_isa_code_density_option=2
20 mpu_version=2
21 nsim_isa_dsp_option=2
26 nsim_isa_dsp_accshift_option=2
34 nsim_isa_xy_y_base=0xe0000000
38 nsim_isa_fpu_fast_mpy_option=0
[all …]
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| D | nsim_em11d.props | 3 arcver=0x3
7 nsim_isa_rgf_num_wr_ports=2
8 nsim_isa_big_endian=0
12 nsim_isa_code_density_option=2
20 mpu_version=2
21 nsim_isa_dsp_option=2
26 nsim_isa_dsp_accshift_option=2
34 nsim_isa_xy_x_base=0xc0000000
35 nsim_isa_xy_y_base=0xe0000000
39 nsim_isa_fpu_fast_mpy_option=0
[all …]
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| D | nsim_em7d_v22.props | 2 nsim_isa_core=2
3 arcver=0x42
7 nsim_isa_big_endian=0
11 nsim_isa_code_density_option=2
18 nsim_isa_dsp_option=2
25 nsim_isa_fpu_fast_mpy_option=0
26 nsim_isa_fpu_fast_div_option=0
30 nsim_isa_timer_1_int_level=0
31 nsim_isa_num_actionpoints=2
36 mpu_version=2
[all …]
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| D | nsim_hs.props | 2 nsim_isa_core=2
3 arcver=0x52
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
8 nsim_isa_big_endian=0
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
26 nsim_isa_timer_1_int_level=0
31 nsim_isa_number_of_levels=2
34 nsim_isa_intvbase_preset=0x0
[all …]
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| D | nsim_hs_mpuv6.props | 2 nsim_isa_core=2
3 arcver=0x52
4 nsim_isa_rgf_num_banks=2
7 nsim_isa_rgf_num_wr_ports=2
8 nsim_isa_big_endian=0
15 nsim_isa_code_density_option=2
16 nsim_isa_div_rem_option=2
28 nsim_isa_timer_1_int_level=0
33 nsim_isa_number_of_levels=2
36 nsim_isa_intvbase_preset=0x0
[all …]
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| D | mdb_em.args | 1 -arcv2em
2 -core3
3 -rgf_num_banks=2
4 -rgf_banked_regs=32
5 -rgf_num_wr_ports=2
6 -Xcode_density
7 -Xdiv_rem=radix2
8 -turbo_boost
9 -Xswap
10 -Xbitscan
[all …]
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| /Zephyr-latest/tests/drivers/build_all/gpio/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
21 reg = <0xdeadbeef 0x1000>;
22 #gpio-cells = <0x2>;
27 compatible = "snps,designware-gpio";
28 gpio-controller;
29 reg = <0xc0ffee 0x1000>;
[all …]
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| /Zephyr-latest/lib/utils/ |
| D | hex.c | 4 * SPDX-License-Identifier: Apache-2.0
14 if ((c >= '0') && (c <= '9')) { in char2hex()
15 *x = c - '0'; in char2hex()
17 *x = c - 'a' + 10; in char2hex()
19 *x = c - 'A' + 10; in char2hex()
21 return -EINVAL; in char2hex()
24 return 0; in char2hex()
30 *c = x + (char)'0'; in hex2char()
32 *c = x - 10 + (char)'a'; in hex2char()
34 return -EINVAL; in hex2char()
[all …]
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| /Zephyr-latest/dts/arm/nordic/ |
| D | nrf54h20_cpurad.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
18 /delete-node/ &cpuapp;
19 /delete-node/ &cpuapp_peripherals;
20 /delete-node/ &cpuapp_ppb;
21 /delete-node/ &cpuapp_ram0;
22 /delete-node/ &cpuppr;
23 /delete-node/ &cpuflpr;
27 compatible = "simple-bus";
28 interrupt-parent = <&cpurad_nvic>;
33 reg = <0xa3000000 0x1000000>;
[all …]
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| /Zephyr-latest/drivers/sensor/st/lps25hb/ |
| D | lps25hb.h | 1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
18 #define LPS25HB_REG_WHO_AM_I 0x0F
19 #define LPS25HB_VAL_WHO_AM_I 0xBD
21 #define LPS25HB_REG_REF_P_XL 0x08
22 #define LPS25HB_REG_REF_P_L 0x09
23 #define LPS25HB_REG_REF_P_H 0x0A
25 #define LPS25HB_REG_RES_CONF 0x10
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
27 #define LPS25HB_SHIFT_RES_CONF_AVGT 2
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| /Zephyr-latest/dts/arm/infineon/cat1a/legacy/ |
| D | psoc6_cm0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
12 cpu@0 {
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
23 reg = <0x40210020 0x20>;
24 ranges = <0x0 0x40210020 0x20>;
26 #address-cells = <1>;
[all …]
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