Lines Matching +full:0 +full:- +full:2

2  * Copyright (c) 2019-2020 Linaro Limited
4  * SPDX-License-Identifier: Apache-2.0
13 #define IOMUX_MAIN_INSEL        (0x868 >> 2)
14 #define IOMUX_MAIN_OUTSEL       (0x870 >> 2)
15 #define IOMUX_MAIN_OENSEL       (0x878 >> 2)
16 #define IOMUX_MAIN_DEFAULT_IN   (0x880 >> 2)
17 #define IOMUX_ALTF1_INSEL       (0x888 >> 2)
18 #define IOMUX_ALTF1_OUTSEL      (0x890 >> 2)
19 #define IOMUX_ALTF1_OENSEL      (0x898 >> 2)
20 #define IOMUX_ALTF1_DEFAULT_IN  (0x8A0 >> 2)
21 #define IOMUX_ALTF2_INSEL       (0x8A8 >> 2)
22 #define IOMUX_ALTF2_OUTSEL      (0x8B0 >> 2)
23 #define IOMUX_ALTF2_OENSEL      (0x8B8 >> 2)
24 #define IOMUX_ALTF2_DEFAULT_IN  (0x8C0 >> 2)
36 	volatile uint32_t *scc = (uint32_t *)DT_REG_ADDR(DT_INST(0, arm_scc));  in arm_musca_s1_pinmux_defaults()
39 	scc[IOMUX_ALTF1_INSEL]  = 0xffff;  in arm_musca_s1_pinmux_defaults()
40 	scc[IOMUX_ALTF1_OUTSEL] = 0xffff;  in arm_musca_s1_pinmux_defaults()
41 	scc[IOMUX_ALTF1_OENSEL] = 0xffff;  in arm_musca_s1_pinmux_defaults()
44 	/* clear bit 0/1 for GPIO0/1 to steer from ALTF1 */  in arm_musca_s1_pinmux_defaults()
45 	scc[IOMUX_MAIN_INSEL]  &= ~(BIT(0) | BIT(1));  in arm_musca_s1_pinmux_defaults()
46 	scc[IOMUX_MAIN_OUTSEL] &= ~(BIT(0) | BIT(1));  in arm_musca_s1_pinmux_defaults()
47 	scc[IOMUX_MAIN_OENSEL] &= ~(BIT(0) | BIT(1));  in arm_musca_s1_pinmux_defaults()
50 	scc[IOMUX_ALTF1_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));  in arm_musca_s1_pinmux_defaults()
51 	scc[IOMUX_ALTF1_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));  in arm_musca_s1_pinmux_defaults()
52 	scc[IOMUX_ALTF2_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));  in arm_musca_s1_pinmux_defaults()
53 	scc[IOMUX_ALTF2_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));  in arm_musca_s1_pinmux_defaults()
62 	return 0;  in arm_musca_pinmux_init()