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/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h3 * @brief Clocks Devicetree macro public API header file.
9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-clocks Devicetree Clocks API
26 * @brief Test if a node has a clocks phandle-array property at a given index
28 * This expands to 1 if the given index is valid clocks property phandle-array index.
33 * n1: node-1 {
34 * clocks = <...>, <...>;
37 * n2: node-2 {
38 * clocks = <...>;
48 * @param node_id node identifier; may or may not have any clocks property
[all …]
/Zephyr-latest/tests/drivers/clock_control/adsp_clock/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
10 static void check_clocks(struct adsp_cpu_clock_info *clocks, uint32_t freq_idx) in check_clocks() argument
16 zassert_equal(clocks[i].current_freq, freq_idx, ""); in check_clocks()
22 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
24 zassert_not_null(clocks, ""); in ZTEST()
27 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
30 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO); in ZTEST()
34 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO); in ZTEST()
40 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
43 zassert_not_null(clocks, ""); in ZTEST()
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/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
12 #include <zephyr/dt-bindings/reset/rp2350_reset.h>
21 die-temp0 = &die_temp;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32bg27.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/clock/silabs/xg27-clock.h>
12 clocks {
14 #clock-cells = <0>;
15 compatible = "fixed-factor-clock";
16 clocks = <&hfxo>;
19 #clock-cells = <0>;
20 compatible = "fixed-factor-clock";
21 clocks = <&hfrcodpll>;
24 #clock-cells = <0>;
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Defr32bg22.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/clock/silabs/xg22-clock.h>
12 clocks {
14 #clock-cells = <0>;
15 compatible = "fixed-factor-clock";
16 clocks = <&em01grpaclk>;
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
25 clock-frequency = <DT_FREQ_M(38)>;
36 interrupt-names = "hfxo";
[all …]
Defr32xg23.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg23-clock.h>
16 zephyr,flash-controller = &msc;
20 clocks {
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
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Defr32mg24.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/adc/adc.h>
11 #include <dt-bindings/clock/silabs/xg24-clock.h>
16 zephyr,flash-controller = &msc;
20 clocks {
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
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/Zephyr-latest/dts/arm/atmel/
Dsamd20.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-0 = &tc0;
12 tc-2 = &tc2;
13 tc-6 = &tc6;
18 compatible = "atmel,sam0-tc32";
21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
22 clock-names = "GCLK", "PM";
27 compatible = "atmel,sam0-tc32";
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
31 clock-names = "GCLK", "PM";
[all …]
Dsaml21.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 tcc-0 = &tcc0;
13 tcc-1 = &tcc1;
14 tcc-2 = &tcc2;
19 compatible = "atmel,sam0-tcc";
22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
23 clock-names = "GCLK", "MCLK";
27 counter-size = <24>;
31 compatible = "atmel,sam0-tcc";
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
[all …]
Dsamd21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-6 = &tc6;
13 tcc-0 = &tcc0;
14 tcc-1 = &tcc1;
15 tcc-2 = &tcc2;
20 compatible = "atmel,sam0-usb";
25 num-bidir-endpoints = <8>;
29 compatible = "atmel,sam0-dmac";
34 #dma-cells = <2>;
38 compatible = "atmel,sam0-tc32";
[all …]
Dsame70.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
21 zephyr,flash-controller = &eefc;
29 #address-cells = <1>;
30 #size-cells = <0>;
[all …]
Dsam4e.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
19 zephyr,flash-controller = &eefc;
23 #address-cells = <1>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-m4f";
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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
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Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
[all …]
Dg4_i2c1_hsi_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
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Df0_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
[all …]
Df3_i2c1_hsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
[all …]
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Clocks clean up config
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
[all …]
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay4 div-m = <8>;
5 mul-n = <100>;
6 div-r = <2>;
7 clocks = <&clk_hse>;
14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
19 pinctrl-0 = <&rcc_mco_1_pa8>;
20 pinctrl-names = "default";
[all …]
Dnucleo_f411re.overlay4 div-m = <8>;
5 mul-n = <100>;
6 div-r = <2>;
7 clocks = <&clk_hse>;
14 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */
19 pinctrl-0 = <&rcc_mco_1_pa8>;
20 pinctrl-names = "default";
[all …]
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/pinctrl/numaker-m46x-pinctrl.h>
10 #include <zephyr/dt-bindings/clock/numaker_m46x_clock.h>
11 #include <zephyr/dt-bindings/reset/numaker_m46x_reset.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
18 zephyr,flash-controller = &fmc;
26 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 clocks {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
24 clocks = <&clk_imo>;
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
[all …]

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