| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
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| D | stm32f1-afio.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #define STM32_REMAP_REG_SHIFT 0U
13 #define STM32_REMAP_SHIFT_SHIFT 1U
15 #define STM32_REMAP_MASK_SHIFT 6U
17 #define STM32_REMAP_VAL_SHIFT 8U
22 * - reg (0/1) [ 0 : 0 ]
23 * - shift (0..31) [ 1 : 5 ]
24 * - mask (0x1, 0x3) [ 6 : 7 ]
25 * - val (0..3) [ 8 : 9 ]
76 #define STM32_AFIO_MAPR 0U
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_ti_cc32xx.c | 3 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
17 10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 255U, 255U, 18U, 19U, 20U,
18 21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
19 255U, 255U, 26U, 27U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U,
20 255U, 255U, 255U, 255U, 255U, 31U, 255U, 255U, 255U, 255U, 0U, 255U, 32U,
21 30U, 255U, 1U, 255U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
29 if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) { in pinctrl_configure_pin()
30 return -EINVAL; in pinctrl_configure_pin()
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U)); in pinctrl_configure_pin()
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | nxp_s32k146_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #define NXP_S32_LPO_128K_CLK 1U
11 #define NXP_S32_SIRC_CLK 2U
12 #define NXP_S32_SIRC_VLP_CLK 3U
13 #define NXP_S32_SIRC_STOP_CLK 4U
14 #define NXP_S32_FIRC_CLK 5U
15 #define NXP_S32_FIRC_VLP_CLK 6U
16 #define NXP_S32_FIRC_STOP_CLK 7U
17 #define NXP_S32_SOSC_CLK 8U
18 #define NXP_S32_SPLL_CLK 9U
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| D | nxp_s32k344_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #define NXP_S32_FIRC_CLK 1U
11 #define NXP_S32_FIRC_STANDBY_CLK 2U
12 #define NXP_S32_SIRC_CLK 3U
13 #define NXP_S32_SIRC_STANDBY_CLK 4U
14 #define NXP_S32_FXOSC_CLK 5U
15 #define NXP_S32_SXOSC_CLK 6U
16 #define NXP_S32_PLL_CLK 7U
17 #define NXP_S32_PLL_POSTDIV_CLK 8U
18 #define NXP_S32_PLL_PHI0_CLK 9U
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| D | nxp_s32z2_clock.h | 2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
10 #define NXP_S32_FIRC_CLK 1U
11 #define NXP_S32_FXOSC_CLK 2U
12 #define NXP_S32_SIRC_CLK 3U
13 #define NXP_S32_COREPLL_CLK 4U
14 #define NXP_S32_PERIPHPLL_CLK 5U
15 #define NXP_S32_DDRPLL_CLK 6U
16 #define NXP_S32_LFAST0_PLL_CLK 7U
17 #define NXP_S32_LFAST1_PLL_CLK 8U
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| D | gd32e50x-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U)
37 #define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U)
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| D | gd32f4xx-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
32 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U)
33 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U)
34 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U)
35 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U)
36 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U)
37 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U)
38 #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U)
39 #define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U)
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| D | gd32e10x-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
39 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
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| D | gd32f403-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
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| D | gd32l23x-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHB1EN, 0U)
30 #define GD32_CLOCK_SRAM0 GD32_CLOCK_CONFIG(AHB1EN, 2U)
31 #define GD32_CLOCK_FMC GD32_CLOCK_CONFIG(AHB1EN, 4U)
32 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 6U)
33 #define GD32_CLOCK_SRAM1 GD32_CLOCK_CONFIG(AHB1EN, 7U)
34 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 17U)
35 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 18U)
36 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 19U)
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| D | gd32a50x-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHBEN, 3U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_MFCOM GD32_CLOCK_CONFIG(AHBEN, 14U)
36 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
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| D | gd32vf103-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
35 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
38 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
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| D | gd32f3x0-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
35 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
36 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U)
37 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U)
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| /Zephyr-latest/soc/microchip/mec/common/ |
| D | soc_pins.h | 4 * SPDX-License-Identifier: Apache-2.0
15 #define MCHP_GPIO_000 (0U)
16 #define MCHP_GPIO_001 (1U)
17 #define MCHP_GPIO_002 (2U)
18 #define MCHP_GPIO_003 (3U)
19 #define MCHP_GPIO_004 (4U)
20 #define MCHP_GPIO_005 (5U)
21 #define MCHP_GPIO_006 (6U)
22 #define MCHP_GPIO_007 (7U)
23 #define MCHP_GPIO_010 (8U)
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| /Zephyr-latest/include/zephyr/dt-bindings/power/ |
| D | imx_scu_rsrc.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #define IMX_SC_R_A53 0U
11 #define IMX_SC_R_A53_0 1U
12 #define IMX_SC_R_A53_1 2U
13 #define IMX_SC_R_A53_2 3U
14 #define IMX_SC_R_A53_3 4U
15 #define IMX_SC_R_A72 5U
16 #define IMX_SC_R_A72_0 6U
17 #define IMX_SC_R_A72_1 7U
18 #define IMX_SC_R_A72_2 8U
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| /Zephyr-latest/subsys/tracing/sysview/ |
| D | tracing_sysview_ids.h | 4 * SPDX-License-Identifier: Apache-2.0
14 #define TID_OFFSET (32u)
16 #define TID_SCHED_LOCK (0u + TID_OFFSET)
17 #define TID_SCHED_UNLOCK (1u + TID_OFFSET)
18 #define TID_BUSYWAIT (2u + TID_OFFSET)
20 #define TID_IRQ_ENABLE (3u + TID_OFFSET)
21 #define TID_IRQ_DISABLE (4u + TID_OFFSET)
23 #define TID_MUTEX_INIT (5u + TID_OFFSET)
24 #define TID_MUTEX_UNLOCK (6u + TID_OFFSET)
25 #define TID_MUTEX_LOCK (7u + TID_OFFSET)
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| /Zephyr-latest/soc/gd/gd32/gd32vf103/ |
| D | nuclei_csr.h | 5 * SPDX-License-Identifier: Apache-2.0
13 * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
31 #define MCOUNTINHIBIT_IR BIT(2U)
32 #define MCOUNTINHIBIT_CY BIT(0U)
34 #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
35 #define MILM_CTL_ILM_RWECC BIT(3U)
36 #define MILM_CTL_ILM_ECC_EXCP_EN BIT(2U)
37 #define MILM_CTL_ILM_ECC_EN BIT(1U)
38 #define MILM_CTL_ILM_EN BIT(0U)
40 #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
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| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | gd32e50x.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
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| D | gd32f4xx.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
32 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U)
33 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U)
34 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U)
35 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U)
36 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U)
37 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U)
38 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U)
39 #define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U)
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| D | gd32f403.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
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| D | gd32e10x.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
37 #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
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| D | gd32a50x.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHBRST, 0U)
31 #define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHBRST, 1U)
32 #define GD32_RESET_SRAMSP GD32_RESET_CONFIG(AHBRST, 2U)
33 #define GD32_RESET_DMAMUX GD32_RESET_CONFIG(AHBRST, 3U)
34 #define GD32_RESET_FMCSP GD32_RESET_CONFIG(AHBRST, 4U)
35 #define GD32_RESET_CRC GD32_RESET_CONFIG(AHBRST, 6U)
36 #define GD32_RESET_MFCOM GD32_RESET_CONFIG(AHBRST, 14U)
37 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
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| D | gd32l23x.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
29 #define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 6U)
30 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 17U)
31 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 18U)
32 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 19U)
33 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 20U)
34 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 22U)
37 #define GD32_RESET_CAU GD32_RESET_CONFIG(AHB2RST, 1U)
38 #define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 3U)
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| /Zephyr-latest/drivers/sensor/adi/adltc2990/ |
| D | adltc2990_reg.h | 2 * SPDX-FileCopyrightText: Copyright (c) 2023 Carl Zeiss Meditec AG
3 * SPDX-License-Identifier: Apache-2.0
26 #define ADLTC2990_VOLTAGE_SINGLE_ENDED_VALUES 2U
27 #define ADLTC2990_VOLTAGE_DIFF_VALUES 1U
28 #define ADLTC2990_TEMP_VALUES 1U
29 #define ADLTC2990_CURRENT_VALUES 1U
30 #define ADLTC2990_MICROOHM_CONVERSION_FACTOR 1000000U
32 #define ADLTC2990_MODE_V1_V2_TR2 0U
33 #define ADLTC2990_MODE_V1_MINUS_V2_TR2 1U
34 #define ADLTC2990_MODE_V1_MINUS_V2_V3_V4 2U
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