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/Zephyr-Core-3.4.0/drivers/disk/
Dsdmmc_sdhc.h1 /* disc_access_sdhc.h - header SDHC*/
6 * SPDX-License-Identifier: Apache-2.0
13 #define SDMMC_CLOCK_400KHZ (400000U)
14 #define SD_CLOCK_25MHZ (25000000U)
15 #define SD_CLOCK_50MHZ (50000000U)
16 #define SD_CLOCK_100MHZ (100000000U)
17 #define SD_CLOCK_208MHZ (208000000U)
18 #define MMC_CLOCK_26MHZ (26000000U)
19 #define MMC_CLOCK_52MHZ (52000000U)
20 #define MMC_CLOCK_DDR52 (52000000U)
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/Zephyr-Core-3.4.0/soc/arm/microchip_mec/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
15 #define MCHP_GPIO_000 (0U)
16 #define MCHP_GPIO_001 (1U)
17 #define MCHP_GPIO_002 (2U)
18 #define MCHP_GPIO_003 (3U)
19 #define MCHP_GPIO_004 (4U)
20 #define MCHP_GPIO_005 (5U)
21 #define MCHP_GPIO_006 (6U)
22 #define MCHP_GPIO_007 (7U)
23 #define MCHP_GPIO_010 (8U)
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/Zephyr-Core-3.4.0/subsys/tracing/sysview/
Dtracing_sysview_ids.h4 * SPDX-License-Identifier: Apache-2.0
14 #define TID_OFFSET (32u)
16 #define TID_SCHED_LOCK (0u + TID_OFFSET)
17 #define TID_SCHED_UNLOCK (1u + TID_OFFSET)
18 #define TID_BUSYWAIT (2u + TID_OFFSET)
20 #define TID_IRQ_ENABLE (3u + TID_OFFSET)
21 #define TID_IRQ_DISABLE (4u + TID_OFFSET)
23 #define TID_MUTEX_INIT (5u + TID_OFFSET)
24 #define TID_MUTEX_UNLOCK (6u + TID_OFFSET)
25 #define TID_MUTEX_LOCK (7u + TID_OFFSET)
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/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/clock/
Dgd32e50x-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U)
37 #define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U)
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Dgd32f4xx-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
32 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U)
33 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U)
34 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U)
35 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U)
36 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U)
37 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U)
38 #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U)
39 #define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U)
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Dgd32e10x-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
39 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
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Dgd32f403-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
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Dgd32l23x-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHB1EN, 0U)
30 #define GD32_CLOCK_SRAM0 GD32_CLOCK_CONFIG(AHB1EN, 2U)
31 #define GD32_CLOCK_FMC GD32_CLOCK_CONFIG(AHB1EN, 4U)
32 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 6U)
33 #define GD32_CLOCK_SRAM1 GD32_CLOCK_CONFIG(AHB1EN, 7U)
34 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 17U)
35 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 18U)
36 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 19U)
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Dgd32a50x-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHBEN, 3U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_MFCOM GD32_CLOCK_CONFIG(AHBEN, 14U)
36 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
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Dgd32vf103-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
35 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
38 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
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Dgd32f3x0-clocks.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
30 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
35 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
36 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U)
37 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U)
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Dkinetis_scg.h4 * SPDX-License-Identifier: Apache-2.0
11 #define KINETIS_SCG_SOSC_MODE_EXT 0U
12 #define KINETIS_SCG_SOSC_MODE_LOW_POWER 4U
13 #define KINETIS_SCG_SOSC_MODE_HIGH_GAIN 12U
16 #define KINETIS_SCG_CORESYS_CLK 0U
17 #define KINETIS_SCG_BUS_CLK 1U
18 #define KINETIS_SCG_FLEXBUS_CLK 2U
19 #define KINETIS_SCG_FLASH_CLK 3U
20 #define KINETIS_SCG_SOSC_CLK 4U
21 #define KINETIS_SCG_SIRC_CLK 5U
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/Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/common/nuclei/
Dnuclei_csr.h5 * SPDX-License-Identifier: Apache-2.0
13 * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
31 #define MCOUNTINHIBIT_IR BIT(2U)
32 #define MCOUNTINHIBIT_CY BIT(0U)
34 #define MILM_CTL_ILM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
35 #define MILM_CTL_ILM_RWECC BIT(3U)
36 #define MILM_CTL_ILM_ECC_EXCP_EN BIT(2U)
37 #define MILM_CTL_ILM_ECC_EN BIT(1U)
38 #define MILM_CTL_ILM_EN BIT(0U)
40 #define MDLM_CTL_DLM_BPA (((1ULL << ((__riscv_xlen) - 10U)) - 1U) << 10U)
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/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/reset/
Dgd32e50x.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
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Dgd32f4xx.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
32 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U)
33 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U)
34 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U)
35 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U)
36 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U)
37 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U)
38 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U)
39 #define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U)
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Dgd32f403.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
37 #define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
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Dgd32e10x.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
32 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
34 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
35 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
36 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
37 #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
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Dgd32a50x.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHBRST, 0U)
31 #define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHBRST, 1U)
32 #define GD32_RESET_SRAMSP GD32_RESET_CONFIG(AHBRST, 2U)
33 #define GD32_RESET_DMAMUX GD32_RESET_CONFIG(AHBRST, 3U)
34 #define GD32_RESET_FMCSP GD32_RESET_CONFIG(AHBRST, 4U)
35 #define GD32_RESET_CRC GD32_RESET_CONFIG(AHBRST, 6U)
36 #define GD32_RESET_MFCOM GD32_RESET_CONFIG(AHBRST, 14U)
37 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
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Dgd32l23x.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
29 #define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 6U)
30 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 17U)
31 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 18U)
32 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 19U)
33 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 20U)
34 #define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 22U)
37 #define GD32_RESET_CAU GD32_RESET_CONFIG(AHB2RST, 1U)
38 #define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 3U)
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Dgd32vf103.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
29 #define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
30 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
31 #define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
32 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
33 #define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
34 #define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
35 #define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
36 #define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
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Dgd32f3x0.h4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
30 #define GD32_RESET_CFGCMP GD32_RESET_CONFIG(APB2RST, 0U)
31 #define GD32_RESET_ADC GD32_RESET_CONFIG(APB2RST, 9U)
32 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
33 #define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
34 #define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
35 #define GD32_RESET_TIMER14 GD32_RESET_CONFIG(APB2RST, 16U)
36 #define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U)
37 #define GD32_RESET_TIMER16 GD32_RESET_CONFIG(APB2RST, 18U)
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/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/pinctrl/
Dstm32f1-afio.h4 * SPDX-License-Identifier: Apache-2.0
11 #define STM32_REMAP_REG_SHIFT 0U
13 #define STM32_REMAP_SHIFT_SHIFT 1U
15 #define STM32_REMAP_MASK_SHIFT 6U
17 #define STM32_REMAP_VAL_SHIFT 8U
22 * - reg (0/1) [ 0 : 0 ]
23 * - shift (0..31) [ 1 : 5 ]
24 * - mask (0x1, 0x3) [ 6 : 7 ]
25 * - val (0..3) [ 8 : 9 ]
76 #define STM32_AFIO_MAPR 0U
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Dnrf-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..16: Pin function.
14 * - 15: Reserved.
15 * - 14: Pin inversion mode.
16 * - 13: Pin low power mode.
17 * - 12..9: Pin output drive configuration.
18 * - 8..7: Pin pull configuration.
19 * - 6..0: Pin number (combination of port and pin).
28 #define NRF_FUN_POS 16U
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/Zephyr-Core-3.4.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
15 #define ESPI_M2SW0_OFS 0u
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
21 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST 0u
25 #define ESPI_M2SW0_MTOS_STATE_POS 12u
28 /* 32-bit word 1 (bits[63:32]) */
29 #define ESPI_M2SW1_OFS 4u
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
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Dmec172x_espi_iom.h4 * SPDX-License-Identifier: Apache-2.0
31 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
38 #define MCHP_ESPI_GBL_CAP1_ALERT_POS 3u /* Read-Only */
41 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 0u
42 #define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4u
45 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
46 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u
47 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u
48 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u
63 * EC sets this bit if it can support open-drain ESPI_ALERT#
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