1 /*
2  * Copyright (c) 2022 Teslabs Engineering S.L.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
9 
10 #include "gd32-clocks-common.h"
11 
12 /**
13  * @name Register offsets
14  * @{
15  */
16 
17 #define GD32_AHBEN_OFFSET        0x14U
18 #define GD32_APB1EN_OFFSET       0x1CU
19 #define GD32_APB2EN_OFFSET       0x18U
20 #define GD32_ADDAPB1EN_OFFSET    0xF8U
21 
22 /** @} */
23 
24 /**
25  * @name Clock enable/disable definitions for peripherals
26  * @{
27  */
28 
29 /* AHB peripherals */
30 #define GD32_CLOCK_DMA        GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_SRAMSP     GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP      GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC        GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_USBFS      GD32_CLOCK_CONFIG(AHBEN, 12U)
35 #define GD32_CLOCK_GPIOA      GD32_CLOCK_CONFIG(AHBEN, 17U)
36 #define GD32_CLOCK_GPIOB      GD32_CLOCK_CONFIG(AHBEN, 18U)
37 #define GD32_CLOCK_GPIOC      GD32_CLOCK_CONFIG(AHBEN, 19U)
38 #define GD32_CLOCK_GPIOD      GD32_CLOCK_CONFIG(AHBEN, 20U)
39 #define GD32_CLOCK_GPIOF      GD32_CLOCK_CONFIG(AHBEN, 22U)
40 #define GD32_CLOCK_TSI        GD32_CLOCK_CONFIG(AHBEN, 24U)
41 
42 /* APB1 peripherals */
43 #define GD32_CLOCK_TIMER1     GD32_CLOCK_CONFIG(APB1EN, 0U)
44 #define GD32_CLOCK_TIMER2     GD32_CLOCK_CONFIG(APB1EN, 1U)
45 #define GD32_CLOCK_TIMER5     GD32_CLOCK_CONFIG(APB1EN, 4U)
46 #define GD32_CLOCK_TIMER13    GD32_CLOCK_CONFIG(APB1EN, 8U)
47 #define GD32_CLOCK_WWDGT      GD32_CLOCK_CONFIG(APB1EN, 11U)
48 #define GD32_CLOCK_SPI1       GD32_CLOCK_CONFIG(APB1EN, 14U)
49 #define GD32_CLOCK_USART1     GD32_CLOCK_CONFIG(APB1EN, 17U)
50 #define GD32_CLOCK_I2C0       GD32_CLOCK_CONFIG(APB1EN, 21U)
51 #define GD32_CLOCK_I2C1       GD32_CLOCK_CONFIG(APB1EN, 22U)
52 #define GD32_CLOCK_PMU        GD32_CLOCK_CONFIG(APB1EN, 28U)
53 #define GD32_CLOCK_DAC        GD32_CLOCK_CONFIG(APB1EN, 29U)
54 #define GD32_CLOCK_CEC        GD32_CLOCK_CONFIG(APB1EN, 30U)
55 
56 /* APB2 peripherals */
57 #define GD32_CLOCK_CFGCMP     GD32_CLOCK_CONFIG(APB2EN, 0U)
58 #define GD32_CLOCK_ADC        GD32_CLOCK_CONFIG(APB2EN, 9U)
59 #define GD32_CLOCK_TIMER0     GD32_CLOCK_CONFIG(APB2EN, 11U)
60 #define GD32_CLOCK_SPI0       GD32_CLOCK_CONFIG(APB2EN, 12U)
61 #define GD32_CLOCK_USART0     GD32_CLOCK_CONFIG(APB2EN, 14U)
62 #define GD32_CLOCK_TIMER14    GD32_CLOCK_CONFIG(APB2EN, 16U)
63 #define GD32_CLOCK_TIMER15    GD32_CLOCK_CONFIG(APB2EN, 17U)
64 #define GD32_CLOCK_TIMER16    GD32_CLOCK_CONFIG(APB2EN, 18U)
65 
66 /* APB1 additional peripherals */
67 #define GD32_CLOCK_CTC        GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
68 
69 /** @} */
70 
71 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ */
72