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/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dti,ina23x-common.yaml4 # SPDX-License-Identifier: Apache-2.0
7 include: [sensor-device.yaml, i2c-device.yaml]
10 current-lsb-microamps:
17 current-lsb(A) = maximum expected current(A) / 2^15
19 (sensor has 15 bits). For example, if maximum expected current is 15A:
21 current-lsb(A) = 15A / 2^15 ~= 457uA
27 rshunt-micro-ohms:
32 alert-gpios:
33 type: phandle-array
Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
16 Current LSB = max expected current [A] / 2^15
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/statistics/src/
Dq7.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
18 #define ABS_ERROR_THRESH_Q31 ((q31_t)(1 << 15))
37 DEFINE_TEST_VARIANT3(statistics_q7, arm_max_q7, 15, in_com1, 0, 15);
59 DEFINE_TEST_VARIANT3(statistics_q7, arm_min_q7, 15, in_com1, 0, 15);
81 DEFINE_TEST_VARIANT3(statistics_q7, arm_absmax_q7, 15, in_absminmax, 0, 15);
103 DEFINE_TEST_VARIANT3(statistics_q7, arm_absmin_q7, 15, in_absminmax, 0, 15);
137 DEFINE_TEST_VARIANT3(statistics_q7, arm_mean_q7, 15, in_com2, 0, 15);
170 DEFINE_TEST_VARIANT3(statistics_q7, arm_power_q7, 15, in_com1, 0, 15);
/Zephyr-latest/soc/altr/zephyr_nios2f/cpu/
Dghrd_10m50da.qsf1 # -------------------------------------------------------------------------- #
3 # Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
18 # -------------------------------------------------------------------------- #
24 # -------------------------------------------------------------------------- #
37 # -------------------------------------------------------------------------- #
40 set_global_assignment -name FAMILY "MAX 10"
41 set_global_assignment -name DEVICE 10M50DAF484C6GES
42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
44 set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/support/src/
Dq7.c3 * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
16 #define REL_ERROR_THRESH (1.0e-5)
41 DEFINE_TEST_VARIANT2(support_q7, arm_copy_q7, 15, in_q7, 15);
68 DEFINE_TEST_VARIANT1(support_q7, arm_fill_q7, 15, 15);
94 DEFINE_TEST_VARIANT3(support_q7, arm_q7_to_float, 15, in_q7, ref_f32, 15);
119 DEFINE_TEST_VARIANT3(support_q7, arm_q7_to_q31, 15, in_q7, ref_q31, 15);
144 DEFINE_TEST_VARIANT3(support_q7, arm_q7_to_q15, 15, in_q7, ref_q15, 15);
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
51 DEFINE_CORRELATE_TEST(14, 15);
56 DEFINE_CORRELATE_TEST(15, 15);
57 DEFINE_CORRELATE_TEST(15, 16);
58 DEFINE_CORRELATE_TEST(15, 17);
59 DEFINE_CORRELATE_TEST(15, 18);
60 DEFINE_CORRELATE_TEST(15, 33);
61 DEFINE_CORRELATE_TEST(16, 15);
66 DEFINE_CORRELATE_TEST(17, 15);
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/Zephyr-latest/dts/bindings/phy/
Dst,stm32u5-otghs-phy.yaml3 # SPDX-License-Identifier: Apache-2.0
6 This binding is to be used by the STM32U5xx transceivers which are built-in
9 compatible: "st,stm32u5-otghs-phy"
11 include: phy-controller.yaml
14 "#phy-cells":
23 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
27 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
31 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
35 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dsam4s_xplained.overlay2 * SPDX-License-Identifier: Apache-2.0
9 io-channels = <&adc0 15>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 reg = <15>;
22 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
24 zephyr,input-positive = <15>;
/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,video-smartdma"
8 include: [base.yaml, pinctrl-device.yaml]
15 vsync-pin:
19 GPIO0 pin index to use for VSYNC input. Only pins 0-15 may be used.
20 hsync-pin:
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
/Zephyr-latest/dts/bindings/pwm/
Dinfineon,xmc4xxx-ccu4-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
12 dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
24 The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
26 slice-prescaler = <15 15 15 15>;
27 pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
28 pinctrl-names = "default";
39 The pin should be configured with drive-push-pull bool option and hwctrl should be set
40 to disabled. The drive-strength field can be set to any of the supported values:
42 drive-strength = "strong-medium-edge";
43 drive-push-pull;
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/Zephyr-latest/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
[all …]
/Zephyr-latest/tests/subsys/dsp/utils/src/
Dq15.c4 * SPDX-License-Identifier: Apache-2.0
24 (-32768, 0, -1.0F), (32767, 0, 0.999969482421875F), (32767, 15, 32767.0F), \
25 (-32768, 15, -32768.0F)
28 (-32768, 0, -1), (32767, 0, 0.999969482421875), (32767, 15, 32767.0), (-32768, 15, -32768.0)
/Zephyr-latest/tests/subsys/dsp/basicmath/src/
Dq7.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
18 #define ABS_ERROR_THRESH_Q31 ((q31_t)(1 << 15))
45 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7, 15, in_com1, in_com2, ref_add, 15);
79 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7_in_place, 15, in_com1, in_com2, ref_add, 15);
114 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7, 15, in_com1, in_com2, ref_sub, 15);
148 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7_in_place, 15, in_com1, in_com2, ref_sub, 15);
183 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_mult_q7, 15, in_com1, in_com2, ref_mult, 15);
217 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_mult_q7_in_place, 15, in_com1, in_com2, ref_mult, 15);
249 DEFINE_TEST_VARIANT3(basic_math_q7, zdsp_negate_q7, 15, in_com1, ref_negate, 15);
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dsam4s_xplained.overlay2 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc0 5>, <&adc0 15>;
15 #address-cells = <1>;
16 #size-cells = <0>;
23 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
24 zephyr,input-positive = <5>;
30 reg = <15>;
33 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
34 zephyr,input-positive = <15>;
/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
47 IPC_EVENT_BIT(15) \
67 [15] = BIT(15),
85 [15] = BIT(15),
/Zephyr-latest/tests/benchmarks/latency_measure/boards/
Dfrdm_k64f.conf2 # allow for a tickless kernel given its 24-bit timer and its 120 MHz
3 # clock rate is 15.
4 CONFIG_SYS_CLOCK_TICKS_PER_SEC=15
/Zephyr-latest/boards/shields/tcan4550evm/
Dtcan4550evm.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
17 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
22 /* reduced spi-max-frequency to accommodate flywire connections */
23 spi-max-frequency = <2000000>;
25 clock-frequency = <40000000>;
26 device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */
27 device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
28 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */
29 int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dnxp,s32-siul2-eirq.yaml1 # Copyright 2022-2024 NXP
3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nxp,s32-siul2-eirq"
9 include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
15 pinctrl-0:
18 pinctrl-names:
21 filter-prescaler:
23 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
31 * IFCP is 0 to 15.
33 child-binding:
[all …]
/Zephyr-latest/boards/st/stm32l496g_disco/
Darduino_r3_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map =
23 <9 0 &gpioh 15 0>, /* D3 */
28 <14 0 &gpiog 15 0>, /* D8 */
29 <15 0 &gpioh 13 0>, /* D9 */
30 <16 0 &gpioa 15 0>, /* D10 */
/Zephyr-latest/dts/bindings/gpio/
Darduino-nano-header-r3.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
11 * A 15-pin Analog Input and power supply header. This has analog input
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
29 8 D8 A1/D15 15
31 10 D10 AREF -
32 11 D11 3V3 -
[all …]
/Zephyr-latest/boards/raytac/mdbt53_db_40/
Draytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
19 low-power-enable;
38 low-power-enable;
47 <NRF_PSEL(UART_CTS, 1, 15)>;
56 <NRF_PSEL(UART_CTS, 1, 15)>;
57 low-power-enable;
70 low-power-enable;
79 <NRF_PSEL(QSPI_IO2, 0, 15)>,
90 <NRF_PSEL(QSPI_IO2, 0, 15)>,
93 low-power-enable;
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/Zephyr-latest/doc/security/media/
Dsensor-model.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
5 …-face font-family="Helvetica" font-size="16" units-per-em="1000" underline-position="-75.68359" un…
6 <font-face-src>
7 <font-face-name name="Helvetica"/>
8 </font-face-src>
9 </font-face>
10 …nits="strokeWidth" id="FilledArrow_Marker" stroke-linejoin="miter" stroke-miterlimit="10" viewBox=…
12 <path d="M 8 0 L 0 -3 L 0 3 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
15 …ts="strokeWidth" id="FilledArrow_Marker_2" stroke-linejoin="miter" stroke-miterlimit="10" viewBox=…
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/Zephyr-latest/dts/bindings/power/
Dnxp,s32-mc-rgm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-mc-rgm"
14 func-reset-threshold:
16 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
17 default: 15
26 dest-reset-threshold:
28 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
34 resets which keeps the chip in the reset state until the next power-on
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]

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