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Searched defs:dmax (Results 1 – 6 of 6) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_dma.h47 #define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt fl… argument
48 #define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt fl… argument
49 #define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt fl… argument
50 #define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt fl… argument
52 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 co… argument
53 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 co… argument
54 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 pe… argument
55 #define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 me… argument
56 #define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 me… argument
57 #define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FI… argument
[all …]
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_dma.h47 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ argument
48 #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear regi… argument
50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control registe… argument
51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter registe… argument
52 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base… argument
53 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base add… argument
55 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control registe… argument
56 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter registe… argument
57 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base… argument
58 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base add… argument
[all …]
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_dma.h47 #define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag regi… argument
48 #define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag clea… argument
50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 control r… argument
51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 counter r… argument
52 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 periphera… argument
53 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 memory ba… argument
55 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 control r… argument
56 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 counter r… argument
57 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 periphera… argument
58 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 memory ba… argument
[all …]
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_dma.h47 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ argument
48 #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear regi… argument
50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control registe… argument
51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter registe… argument
52 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base… argument
53 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base add… argument
55 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control registe… argument
56 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter registe… argument
57 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base… argument
58 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base add… argument
[all …]
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_dma.h48 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ argument
49 #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear regis… argument
50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register… argument
51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register… argument
52 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base … argument
53 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base addr… argument
54 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register… argument
55 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register… argument
56 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base … argument
57 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base addr… argument
[all …]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_dma.h47 #define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt f… argument
48 #define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt f… argument
49 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 c… argument
50 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 c… argument
51 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 p… argument
52 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 m… argument
53 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 c… argument
54 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 c… argument
55 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 p… argument
56 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 m… argument
[all …]