| /Zephyr-Core-3.7.0/soc/nxp/kinetis/k2x/ |
| D | soc.c | 30 #define CLOCK_NODEID(clk) \ argument
33 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/kl2x/ |
| D | soc.c | 17 #define CLOCK_NODEID(clk) \ argument
20 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/kv5x/ |
| D | soc.c | 22 #define CLOCK_NODEID(clk) \ argument
25 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/k6x/ |
| D | soc.c | 32 #define CLOCK_NODEID(clk) \ argument
35 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/kwx/ |
| D | soc_kw4xz.c | 18 #define CLOCK_NODEID(clk) \ argument
21 #define CLOCK_DIVIDER(clk) \ argument
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| D | soc_kw2xd.c | 29 #define CLOCK_NODEID(clk) \ argument
32 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/drivers/serial/ |
| D | uart_pl011_ambiq.h | 22 static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk) in pl011_ambiq_clk_set()
47 static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) in clk_enable_ambiq_uart()
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/k8x/ |
| D | soc.c | 25 #define CLOCK_NODEID(clk) \ argument
28 #define CLOCK_DIVIDER(clk) \ argument
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| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_smartbond.c | 208 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_on() local
260 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_off() local
327 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk) in smartbond_source_clock()
355 static int smartbond_clock_get_rate(enum smartbond_clock clk, uint32_t *rate) in smartbond_clock_get_rate()
418 enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id); in smartbond_clock_control_on_by_ord() local
426 enum smartbond_clock clk = smartbond_dt_ord_to_clock(clock_id); in smartbond_clock_control_off_by_ord() local
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| D | clock_control_adsp.c | 10 static int cavs_clock_ctrl_set_rate(const struct device *clk, in cavs_clock_ctrl_set_rate()
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| D | clock_control_renesas_ra.c | 39 #define CLKSRC_FREQ(clk) DT_PROP(DT_PATH(clocks, clk), clock_frequency) argument
41 #define IS_CLKSRC_ENABLED(clk) DT_NODE_HAS_STATUS(DT_PATH(clocks, clk), okay) argument
45 #define SCKDIV_ENABLED(clk) DT_INST_NODE_HAS_PROP(0, clk##_div) argument
46 #define SCKDIV_VAL(clk) _CONCAT(SCKDIV_, DT_INST_PROP(0, clk##_div)) argument
47 #define SCKDIV_POS(clk) _CONCAT(SCKDIV_POS_, clk) argument
49 #define SCKDIVCR_BITS(clk) \ argument
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| D | clock_control_r8a7795_cpg_mssr.c | 115 static int r8a7795_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a7795_cpg_core_clock_endisable()
150 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a7795_cpg_mssr_start_stop() local
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| D | clock_control_r8a779f0_cpg_mssr.c | 110 static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a779f0_cpg_core_clock_endisable()
144 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a779f0_cpg_mssr_start_stop() local
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| /Zephyr-Core-3.7.0/soc/st/stm32/common/ |
| D | stm32_backup_sram.c | 28 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in stm32_backup_sram_init() local
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| /Zephyr-Core-3.7.0/tests/net/ptp/clock/src/ |
| D | main.c | 308 const struct device *clk; in iface_cb() local
415 const struct device *clk; in test_ptp_clock_interfaces() local
445 const struct device *clk; in test_ptp_clock_iface() local
489 const struct device *clk, *clk_by_index; in test_ptp_clock_get_by_index() local
551 const struct device *clk; in test_ptp_clock_get_kernel() local
568 const struct device *clk; in setup() local
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| /Zephyr-Core-3.7.0/drivers/i2c/ |
| D | i2c_ll_stm32.c | 86 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in i2c_stm32_runtime_configure() local
331 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in i2c_stm32_suspend() local
358 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in i2c_stm32_activate() local
380 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in i2c_stm32_init() local
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| /Zephyr-Core-3.7.0/drivers/usb/device/ |
| D | usb_dc_dw_stm32.h | 22 static inline int clk_enable_st_stm32f4_fsotg(const struct usb_dw_stm32_clk *const clk) in clk_enable_st_stm32f4_fsotg()
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| /Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_i2c.c | 28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock()
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| /Zephyr-Core-3.7.0/drivers/memc/ |
| D | memc_stm32.c | 44 const struct device *clk; in memc_stm32_init() local
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| /Zephyr-Core-3.7.0/drivers/counter/ |
| D | counter_ll_stm32_rtc.c | 189 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in rtc_stm32_start() local
212 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in rtc_stm32_stop() local
552 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in rtc_stm32_init() local
654 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in rtc_stm32_pm_action() local
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| /Zephyr-Core-3.7.0/subsys/net/l2/ethernet/gptp/ |
| D | gptp_user_api.c | 57 const struct device *clk; in gptp_event_capture() local
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| /Zephyr-Core-3.7.0/drivers/watchdog/ |
| D | wdt_wwdg_stm32.c | 92 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in wwdg_stm32_get_pclk() local
282 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in wwdg_stm32_init() local
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| /Zephyr-Core-3.7.0/drivers/fpga/ |
| D | fpga_ice40.c | 92 struct gpio_dt_spec clk; member
139 volatile gpio_port_pins_t *clear, gpio_port_pins_t clk, size_t n) in fpga_ice40_send_clocks()
151 gpio_port_pins_t clk, gpio_port_pins_t pico, uint8_t *z, in fpga_ice40_spi_send_data()
214 gpio_port_pins_t clk; in fpga_ice40_load_gpio() local
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| /Zephyr-Core-3.7.0/drivers/ethernet/ |
| D | eth_native_posix.c | 515 static int ptp_clock_set_native_posix(const struct device *clk, in ptp_clock_set_native_posix()
528 static int ptp_clock_get_native_posix(const struct device *clk, in ptp_clock_get_native_posix()
536 static int ptp_clock_adjust_native_posix(const struct device *clk, in ptp_clock_adjust_native_posix()
549 static int ptp_clock_rate_adjust_native_posix(const struct device *clk, in ptp_clock_rate_adjust_native_posix()
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| /Zephyr-Core-3.7.0/drivers/sensor/st/stm32_digi_temp/ |
| D | stm32_digi_temp.c | 171 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in stm32_digi_temp_init() local
228 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in stm32_digi_temp_pm_action() local
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