1 /*
2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
4 * Copyright (c) 2017, Phytec Messtechnik GmbH
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/device.h>
11 #include <zephyr/init.h>
12 #include <soc.h>
13 #include <zephyr/drivers/uart.h>
14 #include <fsl_common.h>
15 #include <fsl_clock.h>
16
17 #include <cmsis_core.h>
18
19 #define PLLFLLSEL_MCGFLLCLK (0)
20 #define PLLFLLSEL_MCGPLLCLK (1)
21 #define PLLFLLSEL_IRC48MHZ (3)
22
23 #define ER32KSEL_OSC32KCLK (0)
24 #define ER32KSEL_RTC (2)
25 #define ER32KSEL_LPO1KHZ (3)
26
27 #define TIMESRC_OSCERCLK (2)
28
29 #define CLOCK_NODEID(clk) \
30 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
31
32 #define CLOCK_DIVIDER(clk) \
33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
34
35 static const osc_config_t oscConfig = {
36 .freq = CONFIG_OSC_XTAL0_FREQ,
37 .capLoad = 0,
38
39 #if defined(CONFIG_OSC_EXTERNAL)
40 .workMode = kOSC_ModeExt,
41 #elif defined(CONFIG_OSC_LOW_POWER)
42 .workMode = kOSC_ModeOscLowPower,
43 #elif defined(CONFIG_OSC_HIGH_GAIN)
44 .workMode = kOSC_ModeOscHighGain,
45 #else
46 #error "An oscillator mode must be defined"
47 #endif
48
49 .oscerConfig = {
50 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
51 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
52 FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
53 .erclkDiv = 0U,
54 #endif
55 },
56 };
57
58 static const mcg_pll_config_t pll0Config = {
59 .enableMode = 0U,
60 .prdiv = CONFIG_MCG_PRDIV0,
61 .vdiv = CONFIG_MCG_VDIV0,
62 };
63
64 static const sim_clock_config_t simConfig = {
65 .pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
66 .er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
68 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
69 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
70 };
71
72 /**
73 *
74 * @brief Initialize radio transceiver clock output
75 *
76 * The clock output of the transceiver can be used as an input clock
77 * for the PLL of the SoC. The clock output (CLK_OUT) is internally connected
78 * to the input pin EXTAL0 of the SoC. This routine will initialize the clock
79 * output of the transceiver at 4 MHz. The default frequency of the CLK_OUT
80 * depends on the state of GPIO5 during transceiver reset. The frequency
81 * will be 4 MHz if the GPIO5 pin is low, otherwise it will be 32.78689 kHz.
82 *
83 */
set_modem_clock(void)84 static void set_modem_clock(void)
85 {
86 /* Ungate PORTB and PORTC clock */
87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK;
88 /* Set PORTB.19 as output - modem RESET pin */
89 GPIOB->PDDR |= 0x00080000u;
90 /* Set PORTC.0 as output - modem GPIO5 pin */
91 GPIOC->PDDR |= 0x00000001u;
92 /* PORTB.19 as GPIO */
93 PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) |
94 PORT_PCR_MUX(0x01u);
95 /* PORTC.0 as GPIO */
96 PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) |
97 PORT_PCR_MUX(0x01u);
98 /* Clear modem GPIO5 pin */
99 GPIOC->PCOR = 0x00000001u;
100 /* Clear modem RESET pin */
101 GPIOB->PCOR = 0x00080000u;
102 /* Set modem RESET pin */
103 GPIOB->PSOR = 0x00080000u;
104 }
105
106 /**
107 *
108 * @brief Initialize the system clock
109 *
110 * This routine will configure the multipurpose clock generator (MCG) to
111 * set up the system clock.
112 * The MCG has nine possible modes, including Stop mode. This routine assumes
113 * that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
114 * It transitions through the FLL Bypassed External (FBE) and
115 * PLL Bypassed External (PBE) modes to get to the desired
116 * PLL Engaged External (PEE) mode and generate the maximum 48 MHz system
117 * clock.
118 *
119 */
clock_init(void)120 static ALWAYS_INLINE void clock_init(void)
121 {
122 CLOCK_SetSimSafeDivs();
123
124 set_modem_clock();
125
126 CLOCK_InitOsc0(&oscConfig);
127 CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
128
129 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
130
131 CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
132 CONFIG_MCG_FCRDIV);
133
134 CLOCK_SetSimConfig(&simConfig);
135 #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
136 CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
137 DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency));
138 #endif
139 }
140
141 /**
142 *
143 * @brief Perform basic hardware initialization
144 *
145 * Initialize the interrupt controller device drivers.
146 * Also initialize the timer device driver, if required.
147 *
148 * @return 0
149 */
kw2xd_init(void)150 static int kw2xd_init(void)
151 {
152 /* release I/O power hold to allow normal run state */
153 PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
154
155 /* Initialize PLL/system clock to 48 MHz */
156 clock_init();
157
158 return 0;
159 }
160
161 #ifdef CONFIG_PLATFORM_SPECIFIC_INIT
162
z_arm_platform_init(void)163 void z_arm_platform_init(void)
164 {
165 SystemInit();
166 }
167
168 #endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
169
170 SYS_INIT(kw2xd_init, PRE_KERNEL_1, 0);
171
