1 /*
2 * Copyright (c) 2019 SEAL AG
3 *
4 * Based on NXP K6x soc.c, which is:
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
6 * Copyright (c) 2016, Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #include <zephyr/kernel.h>
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <zephyr/cache.h>
15 #include <fsl_common.h>
16 #include <fsl_clock.h>
17
18 #define RUNM_RUN (0)
19 #define RUNM_VLPR (2)
20 #define RUNM_HSRUN (3)
21
22 #define CLOCK_NODEID(clk) \
23 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
24
25 #define CLOCK_DIVIDER(clk) \
26 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
27
28 static const osc_config_t osc_config = {
29 .freq = CONFIG_OSC_XTAL0_FREQ,
30 .capLoad = 0,
31
32 #if defined(CONFIG_OSC_EXTERNAL)
33 .workMode = kOSC_ModeExt,
34 #elif defined(CONFIG_OSC_LOW_POWER)
35 .workMode = kOSC_ModeOscLowPower,
36 #elif defined(CONFIG_OSC_HIGH_GAIN)
37 .workMode = kOSC_ModeOscHighGain,
38 #else
39 #error "An oscillator mode must be defined"
40 #endif
41
42 .oscerConfig = {
43 .enableMode = kOSC_ErClkEnable,
44 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
45 FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
46 .erclkDiv = 0U,
47 #endif
48 },
49 };
50
51 static const mcg_pll_config_t pll0_config = {
52 .enableMode = 0U,
53 .prdiv = CONFIG_MCG_PRDIV0,
54 .vdiv = CONFIG_MCG_VDIV0,
55 };
56
57 static const sim_clock_config_t sim_config = {
58 .pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
59 .er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
60 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
61 SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
62 SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
63 SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
64 };
65
clk_init(void)66 static ALWAYS_INLINE void clk_init(void)
67 {
68 CLOCK_SetSimSafeDivs();
69
70 CLOCK_InitOsc0(&osc_config);
71 CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
72
73 CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0_config);
74
75 CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
76 CONFIG_MCG_FCRDIV);
77
78 CLOCK_SetSimConfig(&sim_config);
79 }
80
kv5x_init(void)81 static int kv5x_init(void)
82 {
83 /* release I/O power hold to allow normal run state */
84 PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
85
86 /* Switch to HSRUN mode */
87 SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK;
88 SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) |
89 SMC_PMCTRL_RUNM(RUNM_HSRUN);
90
91 /* Initialize system clocks and PLL */
92 clk_init();
93
94 sys_cache_instr_enable();
95 sys_cache_data_enable();
96
97 return 0;
98 }
99
100 #ifdef CONFIG_PLATFORM_SPECIFIC_INIT
101
z_arm_platform_init(void)102 void z_arm_platform_init(void)
103 {
104 SystemInit();
105 }
106
107 #endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
108
109 SYS_INIT(kv5x_init, PRE_KERNEL_1, 0);
110
