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Searched defs:PCLK_PASS0_CLOCK_SAR0 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe1m_config.h61 PCLK_PASS0_CLOCK_SAR0 = 0x001Cu, /* pass[0].clock_sar[0] */ enumerator
Dtviibe2m_config.h71 PCLK_PASS0_CLOCK_SAR0 = 0x0026u, /* pass[0].clock_sar[0] */ enumerator
Dtviibe4m_config.h71 PCLK_PASS0_CLOCK_SAR0 = 0x0026u, /* pass[0].clock_sar[0] */ enumerator
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h74 PCLK_PASS0_CLOCK_SAR0 = 0x0123u, /* pass[0].clock_sar[0] */ enumerator
Dtviic2d6m_config.h137 PCLK_PASS0_CLOCK_SAR0 = 0x0114u /* pass[0].clock_sar[0] */ enumerator
Dxmc7200_config.h90 PCLK_PASS0_CLOCK_SAR0 = 0x012Au, /* pass[0].clock_sar[0] */ enumerator