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Searched defs:CONFIG (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_pass_v2.h47 …__IOM uint32_t CONFIG; /*!< 0x00000004 Timer trigger configuration register… member
57 …__IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration r… member
67 __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ member
Dcyip_lpcomp.h42 __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ member
Dcyip_srss_v3.h123 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member
137 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member
171 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
Dcyip_srss_v2.h126 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member
160 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
Dcyip_csd.h42 __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_srss_v3_3.h124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member
134 …__IOM uint32_t CONFIG; /*!< 0x00000000 400MHz Digital PLL Configuration Reg… member
150 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member
184 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
Dcyip_srss_v3_2.h123 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member
137 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member
171 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_lpcomp_v2.h42 __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ member
Dcyip_efuse_v3.h47 __IOM uint32_t CONFIG; /*!< 0x00000114 Config */ member
Dcyip_srss.h124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member
134 __IOM uint32_t CONFIG; /*!< 0x00000000 DPLL_LP Configuration Register */ member