1 /***************************************************************************//** 2 * \file cyip_srss_v3_3.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_V3_3_H_ 28 #define _CYIP_SRSS_V3_3_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define CSV_HF_CSV_SECTION_SIZE 0x00000010UL 37 #define CSV_HF_SECTION_SIZE 0x00000100UL 38 #define CSV_REF_CSV_SECTION_SIZE 0x00000010UL 39 #define CSV_REF_SECTION_SIZE 0x00000010UL 40 #define CSV_LF_CSV_SECTION_SIZE 0x00000010UL 41 #define CSV_LF_SECTION_SIZE 0x00000010UL 42 #define CSV_ILO_CSV_SECTION_SIZE 0x00000010UL 43 #define CSV_ILO_SECTION_SIZE 0x00000010UL 44 #define CLK_PLL400M_SECTION_SIZE 0x00000010UL 45 #define CLK_DPLL400M_SECTION_SIZE 0x00000020UL 46 #define MCWDT_CTR_SECTION_SIZE 0x00000020UL 47 #define MCWDT_SECTION_SIZE 0x00000100UL 48 #define WDT_SECTION_SIZE 0x00000080UL 49 #define SRSS_SECTION_SIZE 0x00010000UL 50 51 /** 52 * \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV) 53 */ 54 typedef struct { 55 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 56 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 57 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 58 __IM uint32_t RESERVED; 59 } CSV_HF_CSV_Type; /*!< Size = 16 (0x10) */ 60 61 /** 62 * \brief Clock Supervisor (CSV) registers for Root clocks (CSV_HF) 63 */ 64 typedef struct { 65 CSV_HF_CSV_Type CSV[16]; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers */ 66 } CSV_HF_Type; /*!< Size = 256 (0x100) */ 67 68 /** 69 * \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV) 70 */ 71 typedef struct { 72 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 73 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 74 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 75 __IM uint32_t RESERVED; 76 } CSV_REF_CSV_Type; /*!< Size = 16 (0x10) */ 77 78 /** 79 * \brief CSV registers for the CSV Reference clock (CSV_REF) 80 */ 81 typedef struct { 82 CSV_REF_CSV_Type CSV; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers for CSV 83 Reference clock */ 84 } CSV_REF_Type; /*!< Size = 16 (0x10) */ 85 86 /** 87 * \brief LF clock Clock Supervisor registers (CSV_LF_CSV) 88 */ 89 typedef struct { 90 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 91 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 92 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 93 __IM uint32_t RESERVED; 94 } CSV_LF_CSV_Type; /*!< Size = 16 (0x10) */ 95 96 /** 97 * \brief CSV registers for LF clock (CSV_LF) 98 */ 99 typedef struct { 100 CSV_LF_CSV_Type CSV; /*!< 0x00000000 LF clock Clock Supervisor registers */ 101 } CSV_LF_Type; /*!< Size = 16 (0x10) */ 102 103 /** 104 * \brief ILO0 clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV) 105 */ 106 typedef struct { 107 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 108 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 109 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 110 __IM uint32_t RESERVED; 111 } CSV_ILO_CSV_Type; /*!< Size = 16 (0x10) */ 112 113 /** 114 * \brief CSV registers for HVILO clock (CSV_ILO) 115 */ 116 typedef struct { 117 CSV_ILO_CSV_Type CSV; /*!< 0x00000000 ILO0 clock DeepSleep domain Clock Supervisor registers */ 118 } CSV_ILO_Type; /*!< Size = 16 (0x10) */ 119 120 /** 121 * \brief 400MHz PLL Configuration Register (CLK_PLL400M) 122 */ 123 typedef struct { 124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ 125 __IOM uint32_t CONFIG2; /*!< 0x00000004 400MHz PLL Configuration Register 2 */ 126 __IOM uint32_t CONFIG3; /*!< 0x00000008 400MHz PLL Configuration Register 3 */ 127 __IOM uint32_t STATUS; /*!< 0x0000000C 400MHz PLL Status Register */ 128 } CLK_PLL400M_Type; /*!< Size = 16 (0x10) */ 129 130 /** 131 * \brief 400MHz Digital PLL Configuration Register (CLK_DPLL400M) 132 */ 133 typedef struct { 134 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz Digital PLL Configuration Register */ 135 __IOM uint32_t CONFIG2; /*!< 0x00000004 400MHz Digital PLL Configuration Register 2 */ 136 __IOM uint32_t CONFIG3; /*!< 0x00000008 400MHz Digital PLL Configuration Register 3 */ 137 __IM uint32_t RESERVED; 138 __IOM uint32_t STATUS; /*!< 0x00000010 400MHz Digital PLL Status Register */ 139 __IM uint32_t RESERVED1[3]; 140 } CLK_DPLL400M_Type; /*!< Size = 32 (0x20) */ 141 142 /** 143 * \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR) 144 */ 145 typedef struct { 146 __IOM uint32_t CTL; /*!< 0x00000000 MCWDT Subcounter Control Register */ 147 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 MCWDT Subcounter Lower Limit Register */ 148 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 MCWDT Subcounter Upper Limit Register */ 149 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C MCWDT Subcounter Warn Limit Register */ 150 __IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Register */ 151 __IOM uint32_t CNT; /*!< 0x00000014 MCWDT Subcounter Count Register */ 152 __IM uint32_t RESERVED[2]; 153 } MCWDT_CTR_Type; /*!< Size = 32 (0x20) */ 154 155 /** 156 * \brief Multi-Counter Watchdog Timer (MCWDT) 157 */ 158 typedef struct { 159 MCWDT_CTR_Type CTR[2]; /*!< 0x00000000 MCWDT Configuration for Subcounter 0 and 1 */ 160 __IOM uint32_t CPU_SELECT; /*!< 0x00000040 MCWDT CPU selection register */ 161 __IM uint32_t RESERVED[15]; 162 __IOM uint32_t CTR2_CTL; /*!< 0x00000080 MCWDT Subcounter 2 Control register */ 163 __IOM uint32_t CTR2_CONFIG; /*!< 0x00000084 MCWDT Subcounter 2 Configuration register */ 164 __IOM uint32_t CTR2_CNT; /*!< 0x00000088 MCWDT Subcounter 2 Count Register */ 165 __IM uint32_t RESERVED1; 166 __IOM uint32_t LOCK; /*!< 0x00000090 MCWDT Lock Register */ 167 __IOM uint32_t SERVICE; /*!< 0x00000094 MCWDT Service Register */ 168 __IM uint32_t RESERVED2[2]; 169 __IOM uint32_t INTR; /*!< 0x000000A0 MCWDT Interrupt Register */ 170 __IOM uint32_t INTR_SET; /*!< 0x000000A4 MCWDT Interrupt Set Register */ 171 __IOM uint32_t INTR_MASK; /*!< 0x000000A8 MCWDT Interrupt Mask Register */ 172 __IM uint32_t INTR_MASKED; /*!< 0x000000AC MCWDT Interrupt Masked Register */ 173 __IM uint32_t RESERVED3[20]; 174 } MCWDT_Type; /*!< Size = 256 (0x100) */ 175 176 /** 177 * \brief Watchdog Timer (WDT) 178 */ 179 typedef struct { 180 __IOM uint32_t CTL; /*!< 0x00000000 WDT Control Register */ 181 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 WDT Lower Limit Register */ 182 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 WDT Upper Limit Register */ 183 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C WDT Warn Limit Register */ 184 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ 185 __IOM uint32_t CNT; /*!< 0x00000014 WDT Count Register */ 186 __IM uint32_t RESERVED[10]; 187 __IOM uint32_t LOCK; /*!< 0x00000040 WDT Lock register */ 188 __IOM uint32_t SERVICE; /*!< 0x00000044 WDT Service register */ 189 __IM uint32_t RESERVED1[2]; 190 __IOM uint32_t INTR; /*!< 0x00000050 WDT Interrupt Register */ 191 __IOM uint32_t INTR_SET; /*!< 0x00000054 WDT Interrupt Set Register */ 192 __IOM uint32_t INTR_MASK; /*!< 0x00000058 WDT Interrupt Mask Register */ 193 __IM uint32_t INTR_MASKED; /*!< 0x0000005C WDT Interrupt Masked Register */ 194 __IM uint32_t RESERVED2[8]; 195 } WDT_Type; /*!< Size = 128 (0x80) */ 196 197 /** 198 * \brief SRSS Core Registers (ver3p3) (SRSS) 199 */ 200 typedef struct { 201 __IM uint32_t RESERVED[16]; 202 __IM uint32_t PWR_LVD_STATUS; /*!< 0x00000040 High Voltage / Low Voltage Detector (HVLVD) Status Register */ 203 __IM uint32_t PWR_LVD_STATUS2; /*!< 0x00000044 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 */ 204 __IM uint32_t RESERVED1[46]; 205 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000100 Clock DSI Select Register */ 206 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000140 Fast Clock Output Select Register */ 207 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000144 Slow Clock Output Select Register */ 208 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x00000148 Clock Calibration Counter 1 */ 209 __IM uint32_t CLK_CAL_CNT2; /*!< 0x0000014C Clock Calibration Counter 2 */ 210 __IM uint32_t RESERVED2[44]; 211 __IOM uint32_t SRSS_INTR; /*!< 0x00000200 SRSS Interrupt Register */ 212 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000204 SRSS Interrupt Set Register */ 213 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000208 SRSS Interrupt Mask Register */ 214 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000020C SRSS Interrupt Masked Register */ 215 __IM uint32_t RESERVED3[892]; 216 __IM uint32_t PWR_CTL; /*!< 0x00001000 Power Mode Control */ 217 __IOM uint32_t PWR_CTL2; /*!< 0x00001004 Power Mode Control 2 */ 218 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00001008 HIBERNATE Mode Register */ 219 __IM uint32_t RESERVED4; 220 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00001010 Buck Control Register */ 221 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00001014 Buck Control Register 2 */ 222 __IOM uint32_t PWR_SSV_CTL; /*!< 0x00001018 Supply Supervision Control Register */ 223 __IM uint32_t PWR_SSV_STATUS; /*!< 0x0000101C Supply Supervision Status Register */ 224 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration 225 Register */ 226 __IOM uint32_t PWR_LVD_CTL2; /*!< 0x00001024 High Voltage / Low Voltage Detector (HVLVD) Configuration 227 Register #2 */ 228 __IOM uint32_t PWR_REGHC_CTL; /*!< 0x00001028 REGHC Control Register */ 229 __IM uint32_t PWR_REGHC_STATUS; /*!< 0x0000102C REGHC Status Register */ 230 __IOM uint32_t PWR_REGHC_CTL2; /*!< 0x00001030 REGHC Control Register 2 */ 231 __IM uint32_t RESERVED5; 232 __IOM uint32_t PWR_REGHC_CTL4; /*!< 0x00001038 REGHC Control Register 4 */ 233 __IM uint32_t RESERVED6; 234 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00001040 HIBERNATE Data Register */ 235 __IM uint32_t RESERVED7[16]; 236 __IOM uint32_t PWR_PMIC_CTL; /*!< 0x000010C0 PMIC Control Register */ 237 __IM uint32_t PWR_PMIC_STATUS; /*!< 0x000010C4 PMIC Status Register */ 238 __IOM uint32_t PWR_PMIC_CTL2; /*!< 0x000010C8 PMIC Control Register 2 */ 239 __IM uint32_t RESERVED8; 240 __IOM uint32_t PWR_PMIC_CTL4; /*!< 0x000010D0 PMIC Control Register 4 */ 241 __IM uint32_t RESERVED9[3]; 242 __IOM uint32_t PWR_HIB_WAKE_CTL; /*!< 0x000010E0 Hibernate Wakeup Mask Register */ 243 __IOM uint32_t PWR_HIB_WAKE_CTL2; /*!< 0x000010E4 Hibernate Wakeup Polarity Register */ 244 __IM uint32_t RESERVED10; 245 __IOM uint32_t PWR_HIB_WAKE_CAUSE; /*!< 0x000010EC Hibernate Wakeup Cause Register */ 246 __IM uint32_t RESERVED11[68]; 247 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00001200 Clock Path Select Register */ 248 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00001240 Clock Root Select Register */ 249 __IM uint32_t RESERVED12[96]; 250 CSV_HF_Type CSV_HF; /*!< 0x00001400 Clock Supervisor (CSV) registers for Root clocks */ 251 __IOM uint32_t CLK_SELECT; /*!< 0x00001500 Clock selection register */ 252 __IM uint32_t RESERVED13; 253 __IOM uint32_t CLK_ILO0_CONFIG; /*!< 0x00001508 ILO0 Configuration */ 254 __IOM uint32_t CLK_ILO1_CONFIG; /*!< 0x0000150C ILO1 Configuration */ 255 __IM uint32_t RESERVED14[2]; 256 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00001518 IMO Configuration */ 257 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000151C ECO Configuration Register */ 258 __IOM uint32_t CLK_ECO_PRESCALE; /*!< 0x00001520 ECO Prescaler Configuration Register */ 259 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00001524 ECO Status Register */ 260 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x00001528 Precision ILO Configuration Register */ 261 __IM uint32_t RESERVED15; 262 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00001530 FLL Configuration Register */ 263 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00001534 FLL Configuration Register 2 */ 264 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00001538 FLL Configuration Register 3 */ 265 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000153C FLL Configuration Register 4 */ 266 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00001540 FLL Status Register */ 267 __IOM uint32_t CLK_ECO_CONFIG2; /*!< 0x00001544 ECO Configuration Register 2 */ 268 __IM uint32_t RESERVED16[46]; 269 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00001600 PLL Configuration Register */ 270 __IM uint32_t RESERVED17; 271 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00001640 PLL Status Register */ 272 __IM uint32_t RESERVED18[33]; 273 __IOM uint32_t CSV_REF_SEL; /*!< 0x00001700 Select CSV Reference clock for Active domain */ 274 __IM uint32_t RESERVED19[3]; 275 CSV_REF_Type CSV_REF; /*!< 0x00001710 CSV registers for the CSV Reference clock */ 276 CSV_LF_Type CSV_LF; /*!< 0x00001720 CSV registers for LF clock */ 277 CSV_ILO_Type CSV_ILO; /*!< 0x00001730 CSV registers for HVILO clock */ 278 __IM uint32_t RESERVED20[48]; 279 __IOM uint32_t RES_CAUSE; /*!< 0x00001800 Reset Cause Observation Register */ 280 __IOM uint32_t RES_CAUSE2; /*!< 0x00001804 Reset Cause Observation Register 2 */ 281 __IM uint32_t RESERVED21[62]; 282 CLK_PLL400M_Type CLK_PLL400M[15]; /*!< 0x00001900 400MHz PLL Configuration Register */ 283 __IM uint32_t RESERVED22[4]; 284 CLK_DPLL400M_Type CLK_DPLL400M[15]; /*!< 0x00001A00 400MHz Digital PLL Configuration Register */ 285 __IM uint32_t RESERVED23[1293]; 286 __IOM uint32_t CLK_TRIM_ILO0_CTL; /*!< 0x00003014 ILO0 Trim Register */ 287 __IM uint32_t RESERVED24[60]; 288 __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x00003108 Power System Trim Register */ 289 __IM uint32_t RESERVED25[2]; 290 __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x00003114 PILO Trim Register */ 291 __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x00003118 PILO Trim Register 2 */ 292 __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000311C PILO Trim Register 3 */ 293 __IM uint32_t RESERVED26[64]; 294 __IOM uint32_t CLK_TRIM_ILO1_CTL; /*!< 0x00003220 ILO1 Trim Register */ 295 __IM uint32_t RESERVED27[4983]; 296 MCWDT_Type MCWDT[4]; /*!< 0x00008000 Multi-Counter Watchdog Timer */ 297 __IM uint32_t RESERVED28[3840]; 298 WDT_Type WDT_STRUCT; /*!< 0x0000C000 Watchdog Timer */ 299 } SRSS_Type; /*!< Size = 49280 (0xC080) */ 300 301 302 /* CSV_HF_CSV.REF_CTL */ 303 #define CSV_HF_CSV_REF_CTL_STARTUP_Pos 0UL 304 #define CSV_HF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 305 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 306 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 307 #define CSV_HF_CSV_REF_CTL_CSV_EN_Pos 31UL 308 #define CSV_HF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 309 /* CSV_HF_CSV.REF_LIMIT */ 310 #define CSV_HF_CSV_REF_LIMIT_LOWER_Pos 0UL 311 #define CSV_HF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 312 #define CSV_HF_CSV_REF_LIMIT_UPPER_Pos 16UL 313 #define CSV_HF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 314 /* CSV_HF_CSV.MON_CTL */ 315 #define CSV_HF_CSV_MON_CTL_PERIOD_Pos 0UL 316 #define CSV_HF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 317 318 319 /* CSV_REF_CSV.REF_CTL */ 320 #define CSV_REF_CSV_REF_CTL_STARTUP_Pos 0UL 321 #define CSV_REF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 322 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 323 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 324 #define CSV_REF_CSV_REF_CTL_CSV_EN_Pos 31UL 325 #define CSV_REF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 326 /* CSV_REF_CSV.REF_LIMIT */ 327 #define CSV_REF_CSV_REF_LIMIT_LOWER_Pos 0UL 328 #define CSV_REF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 329 #define CSV_REF_CSV_REF_LIMIT_UPPER_Pos 16UL 330 #define CSV_REF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 331 /* CSV_REF_CSV.MON_CTL */ 332 #define CSV_REF_CSV_MON_CTL_PERIOD_Pos 0UL 333 #define CSV_REF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 334 335 336 /* CSV_LF_CSV.REF_CTL */ 337 #define CSV_LF_CSV_REF_CTL_STARTUP_Pos 0UL 338 #define CSV_LF_CSV_REF_CTL_STARTUP_Msk 0x1FFUL 339 #define CSV_LF_CSV_REF_CTL_CSV_EN_Pos 31UL 340 #define CSV_LF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 341 /* CSV_LF_CSV.REF_LIMIT */ 342 #define CSV_LF_CSV_REF_LIMIT_LOWER_Pos 0UL 343 #define CSV_LF_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 344 #define CSV_LF_CSV_REF_LIMIT_UPPER_Pos 16UL 345 #define CSV_LF_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 346 /* CSV_LF_CSV.MON_CTL */ 347 #define CSV_LF_CSV_MON_CTL_PERIOD_Pos 0UL 348 #define CSV_LF_CSV_MON_CTL_PERIOD_Msk 0xFFUL 349 350 351 /* CSV_ILO_CSV.REF_CTL */ 352 #define CSV_ILO_CSV_REF_CTL_STARTUP_Pos 0UL 353 #define CSV_ILO_CSV_REF_CTL_STARTUP_Msk 0x1FFUL 354 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Pos 31UL 355 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 356 /* CSV_ILO_CSV.REF_LIMIT */ 357 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Pos 0UL 358 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 359 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Pos 16UL 360 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 361 /* CSV_ILO_CSV.MON_CTL */ 362 #define CSV_ILO_CSV_MON_CTL_PERIOD_Pos 0UL 363 #define CSV_ILO_CSV_MON_CTL_PERIOD_Msk 0xFFUL 364 365 366 /* CLK_PLL400M.CONFIG */ 367 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos 0UL 368 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 369 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos 8UL 370 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 371 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos 16UL 372 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 373 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Pos 25UL 374 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Msk 0x6000000UL 375 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Pos 28UL 376 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Msk 0x30000000UL 377 #define CLK_PLL400M_CONFIG_ENABLE_Pos 31UL 378 #define CLK_PLL400M_CONFIG_ENABLE_Msk 0x80000000UL 379 /* CLK_PLL400M.CONFIG2 */ 380 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Pos 0UL 381 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 382 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Pos 28UL 383 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 384 #define CLK_PLL400M_CONFIG2_FRAC_EN_Pos 31UL 385 #define CLK_PLL400M_CONFIG2_FRAC_EN_Msk 0x80000000UL 386 /* CLK_PLL400M.CONFIG3 */ 387 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Pos 0UL 388 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 389 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Pos 16UL 390 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Msk 0x70000UL 391 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Pos 24UL 392 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 393 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Pos 28UL 394 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Msk 0x10000000UL 395 #define CLK_PLL400M_CONFIG3_SSCG_EN_Pos 31UL 396 #define CLK_PLL400M_CONFIG3_SSCG_EN_Msk 0x80000000UL 397 /* CLK_PLL400M.STATUS */ 398 #define CLK_PLL400M_STATUS_LOCKED_Pos 0UL 399 #define CLK_PLL400M_STATUS_LOCKED_Msk 0x1UL 400 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Pos 1UL 401 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 402 403 404 /* CLK_DPLL400M.CONFIG */ 405 #define CLK_DPLL400M_CONFIG_FEEDBACK_DIV_Pos 0UL 406 #define CLK_DPLL400M_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 407 #define CLK_DPLL400M_CONFIG_REFERENCE_DIV_Pos 8UL 408 #define CLK_DPLL400M_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 409 #define CLK_DPLL400M_CONFIG_OUTPUT_DIV_Pos 16UL 410 #define CLK_DPLL400M_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 411 #define CLK_DPLL400M_CONFIG_LOCK_DELAY_Pos 25UL 412 #define CLK_DPLL400M_CONFIG_LOCK_DELAY_Msk 0x6000000UL 413 #define CLK_DPLL400M_CONFIG_BYPASS_SEL_Pos 28UL 414 #define CLK_DPLL400M_CONFIG_BYPASS_SEL_Msk 0x30000000UL 415 #define CLK_DPLL400M_CONFIG_ENABLE_Pos 31UL 416 #define CLK_DPLL400M_CONFIG_ENABLE_Msk 0x80000000UL 417 /* CLK_DPLL400M.CONFIG2 */ 418 #define CLK_DPLL400M_CONFIG2_FRAC_DIV_Pos 0UL 419 #define CLK_DPLL400M_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 420 #define CLK_DPLL400M_CONFIG2_FRAC_DITHER_EN_Pos 28UL 421 #define CLK_DPLL400M_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 422 #define CLK_DPLL400M_CONFIG2_FRAC_EN_Pos 31UL 423 #define CLK_DPLL400M_CONFIG2_FRAC_EN_Msk 0x80000000UL 424 /* CLK_DPLL400M.CONFIG3 */ 425 #define CLK_DPLL400M_CONFIG3_SSCG_DEPTH_Pos 0UL 426 #define CLK_DPLL400M_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 427 #define CLK_DPLL400M_CONFIG3_SSCG_RATE_Pos 16UL 428 #define CLK_DPLL400M_CONFIG3_SSCG_RATE_Msk 0x70000UL 429 #define CLK_DPLL400M_CONFIG3_SSCG_DITHER_EN_Pos 24UL 430 #define CLK_DPLL400M_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 431 #define CLK_DPLL400M_CONFIG3_SSCG_MODE_Pos 28UL 432 #define CLK_DPLL400M_CONFIG3_SSCG_MODE_Msk 0x10000000UL 433 #define CLK_DPLL400M_CONFIG3_SSCG_EN_Pos 31UL 434 #define CLK_DPLL400M_CONFIG3_SSCG_EN_Msk 0x80000000UL 435 /* CLK_DPLL400M.STATUS */ 436 #define CLK_DPLL400M_STATUS_LOCKED_Pos 0UL 437 #define CLK_DPLL400M_STATUS_LOCKED_Msk 0x1UL 438 #define CLK_DPLL400M_STATUS_UNLOCK_OCCURRED_Pos 1UL 439 #define CLK_DPLL400M_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 440 441 442 /* MCWDT_CTR.CTL */ 443 #define MCWDT_CTR_CTL_ENABLED_Pos 0UL 444 #define MCWDT_CTR_CTL_ENABLED_Msk 0x1UL 445 #define MCWDT_CTR_CTL_ENABLE_Pos 31UL 446 #define MCWDT_CTR_CTL_ENABLE_Msk 0x80000000UL 447 /* MCWDT_CTR.LOWER_LIMIT */ 448 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 449 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFUL 450 /* MCWDT_CTR.UPPER_LIMIT */ 451 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 452 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFUL 453 /* MCWDT_CTR.WARN_LIMIT */ 454 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos 0UL 455 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFUL 456 /* MCWDT_CTR.CONFIG */ 457 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos 0UL 458 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk 0x3UL 459 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos 4UL 460 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk 0x30UL 461 #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos 8UL 462 #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk 0x100UL 463 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos 12UL 464 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk 0x1000UL 465 #define MCWDT_CTR_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 466 #define MCWDT_CTR_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 467 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 468 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 469 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos 31UL 470 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk 0x80000000UL 471 /* MCWDT_CTR.CNT */ 472 #define MCWDT_CTR_CNT_CNT_Pos 0UL 473 #define MCWDT_CTR_CNT_CNT_Msk 0xFFFFUL 474 475 476 /* MCWDT.CPU_SELECT */ 477 #define MCWDT_CPU_SELECT_CPU_SEL_Pos 0UL 478 #define MCWDT_CPU_SELECT_CPU_SEL_Msk 0x3UL 479 /* MCWDT.CTR2_CTL */ 480 #define MCWDT_CTR2_CTL_ENABLED_Pos 0UL 481 #define MCWDT_CTR2_CTL_ENABLED_Msk 0x1UL 482 #define MCWDT_CTR2_CTL_ENABLE_Pos 31UL 483 #define MCWDT_CTR2_CTL_ENABLE_Msk 0x80000000UL 484 /* MCWDT.CTR2_CONFIG */ 485 #define MCWDT_CTR2_CONFIG_ACTION_Pos 0UL 486 #define MCWDT_CTR2_CONFIG_ACTION_Msk 0x1UL 487 #define MCWDT_CTR2_CONFIG_BITS_Pos 16UL 488 #define MCWDT_CTR2_CONFIG_BITS_Msk 0x1F0000UL 489 #define MCWDT_CTR2_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 490 #define MCWDT_CTR2_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 491 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 492 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 493 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos 31UL 494 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk 0x80000000UL 495 /* MCWDT.CTR2_CNT */ 496 #define MCWDT_CTR2_CNT_CNT2_Pos 0UL 497 #define MCWDT_CTR2_CNT_CNT2_Msk 0xFFFFFFFFUL 498 /* MCWDT.LOCK */ 499 #define MCWDT_LOCK_MCWDT_LOCK_Pos 0UL 500 #define MCWDT_LOCK_MCWDT_LOCK_Msk 0x3UL 501 /* MCWDT.SERVICE */ 502 #define MCWDT_SERVICE_CTR0_SERVICE_Pos 0UL 503 #define MCWDT_SERVICE_CTR0_SERVICE_Msk 0x1UL 504 #define MCWDT_SERVICE_CTR1_SERVICE_Pos 1UL 505 #define MCWDT_SERVICE_CTR1_SERVICE_Msk 0x2UL 506 /* MCWDT.INTR */ 507 #define MCWDT_INTR_CTR0_INT_Pos 0UL 508 #define MCWDT_INTR_CTR0_INT_Msk 0x1UL 509 #define MCWDT_INTR_CTR1_INT_Pos 1UL 510 #define MCWDT_INTR_CTR1_INT_Msk 0x2UL 511 #define MCWDT_INTR_CTR2_INT_Pos 2UL 512 #define MCWDT_INTR_CTR2_INT_Msk 0x4UL 513 /* MCWDT.INTR_SET */ 514 #define MCWDT_INTR_SET_CTR0_INT_Pos 0UL 515 #define MCWDT_INTR_SET_CTR0_INT_Msk 0x1UL 516 #define MCWDT_INTR_SET_CTR1_INT_Pos 1UL 517 #define MCWDT_INTR_SET_CTR1_INT_Msk 0x2UL 518 #define MCWDT_INTR_SET_CTR2_INT_Pos 2UL 519 #define MCWDT_INTR_SET_CTR2_INT_Msk 0x4UL 520 /* MCWDT.INTR_MASK */ 521 #define MCWDT_INTR_MASK_CTR0_INT_Pos 0UL 522 #define MCWDT_INTR_MASK_CTR0_INT_Msk 0x1UL 523 #define MCWDT_INTR_MASK_CTR1_INT_Pos 1UL 524 #define MCWDT_INTR_MASK_CTR1_INT_Msk 0x2UL 525 #define MCWDT_INTR_MASK_CTR2_INT_Pos 2UL 526 #define MCWDT_INTR_MASK_CTR2_INT_Msk 0x4UL 527 /* MCWDT.INTR_MASKED */ 528 #define MCWDT_INTR_MASKED_CTR0_INT_Pos 0UL 529 #define MCWDT_INTR_MASKED_CTR0_INT_Msk 0x1UL 530 #define MCWDT_INTR_MASKED_CTR1_INT_Pos 1UL 531 #define MCWDT_INTR_MASKED_CTR1_INT_Msk 0x2UL 532 #define MCWDT_INTR_MASKED_CTR2_INT_Pos 2UL 533 #define MCWDT_INTR_MASKED_CTR2_INT_Msk 0x4UL 534 535 536 /* WDT.CTL */ 537 #define WDT_CTL_ENABLED_Pos 0UL 538 #define WDT_CTL_ENABLED_Msk 0x1UL 539 #define WDT_CTL_ENABLE_Pos 31UL 540 #define WDT_CTL_ENABLE_Msk 0x80000000UL 541 /* WDT.LOWER_LIMIT */ 542 #define WDT_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 543 #define WDT_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFFFFFUL 544 /* WDT.UPPER_LIMIT */ 545 #define WDT_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 546 #define WDT_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFFFFFUL 547 /* WDT.WARN_LIMIT */ 548 #define WDT_WARN_LIMIT_WARN_LIMIT_Pos 0UL 549 #define WDT_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFFFFFUL 550 /* WDT.CONFIG */ 551 #define WDT_CONFIG_LOWER_ACTION_Pos 0UL 552 #define WDT_CONFIG_LOWER_ACTION_Msk 0x1UL 553 #define WDT_CONFIG_UPPER_ACTION_Pos 4UL 554 #define WDT_CONFIG_UPPER_ACTION_Msk 0x10UL 555 #define WDT_CONFIG_WARN_ACTION_Pos 8UL 556 #define WDT_CONFIG_WARN_ACTION_Msk 0x100UL 557 #define WDT_CONFIG_AUTO_SERVICE_Pos 12UL 558 #define WDT_CONFIG_AUTO_SERVICE_Msk 0x1000UL 559 #define WDT_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 560 #define WDT_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 561 #define WDT_CONFIG_DPSLP_PAUSE_Pos 29UL 562 #define WDT_CONFIG_DPSLP_PAUSE_Msk 0x20000000UL 563 #define WDT_CONFIG_HIB_PAUSE_Pos 30UL 564 #define WDT_CONFIG_HIB_PAUSE_Msk 0x40000000UL 565 #define WDT_CONFIG_DEBUG_RUN_Pos 31UL 566 #define WDT_CONFIG_DEBUG_RUN_Msk 0x80000000UL 567 /* WDT.CNT */ 568 #define WDT_CNT_CNT_Pos 0UL 569 #define WDT_CNT_CNT_Msk 0xFFFFFFFFUL 570 /* WDT.LOCK */ 571 #define WDT_LOCK_WDT_LOCK_Pos 0UL 572 #define WDT_LOCK_WDT_LOCK_Msk 0x3UL 573 /* WDT.SERVICE */ 574 #define WDT_SERVICE_SERVICE_Pos 0UL 575 #define WDT_SERVICE_SERVICE_Msk 0x1UL 576 /* WDT.INTR */ 577 #define WDT_INTR_WDT_Pos 0UL 578 #define WDT_INTR_WDT_Msk 0x1UL 579 /* WDT.INTR_SET */ 580 #define WDT_INTR_SET_WDT_Pos 0UL 581 #define WDT_INTR_SET_WDT_Msk 0x1UL 582 /* WDT.INTR_MASK */ 583 #define WDT_INTR_MASK_WDT_Pos 0UL 584 #define WDT_INTR_MASK_WDT_Msk 0x1UL 585 /* WDT.INTR_MASKED */ 586 #define WDT_INTR_MASKED_WDT_Pos 0UL 587 #define WDT_INTR_MASKED_WDT_Msk 0x1UL 588 589 590 /* SRSS.PWR_LVD_STATUS */ 591 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos 0UL 592 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk 0x1UL 593 /* SRSS.PWR_LVD_STATUS2 */ 594 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 0UL 595 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 0x1UL 596 /* SRSS.CLK_DSI_SELECT */ 597 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 598 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 599 /* SRSS.CLK_OUTPUT_FAST */ 600 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 601 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 602 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 603 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 604 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 605 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 606 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 607 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 608 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 609 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 610 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 611 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 612 /* SRSS.CLK_OUTPUT_SLOW */ 613 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 614 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 615 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 616 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 617 /* SRSS.CLK_CAL_CNT1 */ 618 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 619 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 620 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 621 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 622 /* SRSS.CLK_CAL_CNT2 */ 623 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 624 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 625 /* SRSS.SRSS_INTR */ 626 #define SRSS_SRSS_INTR_HVLVD1_Pos 1UL 627 #define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL 628 #define SRSS_SRSS_INTR_HVLVD2_Pos 2UL 629 #define SRSS_SRSS_INTR_HVLVD2_Msk 0x4UL 630 #define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL 631 #define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL 632 /* SRSS.SRSS_INTR_SET */ 633 #define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL 634 #define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL 635 #define SRSS_SRSS_INTR_SET_HVLVD2_Pos 2UL 636 #define SRSS_SRSS_INTR_SET_HVLVD2_Msk 0x4UL 637 #define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL 638 #define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 639 /* SRSS.SRSS_INTR_MASK */ 640 #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL 641 #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL 642 #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos 2UL 643 #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk 0x4UL 644 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 645 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 646 /* SRSS.SRSS_INTR_MASKED */ 647 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL 648 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL 649 #define SRSS_SRSS_INTR_MASKED_HVLVD2_Pos 2UL 650 #define SRSS_SRSS_INTR_MASKED_HVLVD2_Msk 0x4UL 651 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 652 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 653 /* SRSS.PWR_CTL */ 654 #define SRSS_PWR_CTL_POWER_MODE_Pos 0UL 655 #define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL 656 #define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL 657 #define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 658 #define SRSS_PWR_CTL_LPM_READY_Pos 5UL 659 #define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL 660 /* SRSS.PWR_CTL2 */ 661 #define SRSS_PWR_CTL2_LINREG_DIS_Pos 0UL 662 #define SRSS_PWR_CTL2_LINREG_DIS_Msk 0x1UL 663 #define SRSS_PWR_CTL2_LINREG_OK_Pos 1UL 664 #define SRSS_PWR_CTL2_LINREG_OK_Msk 0x2UL 665 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos 2UL 666 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk 0x4UL 667 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos 4UL 668 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk 0x10UL 669 #define SRSS_PWR_CTL2_RET_REG_DIS_Pos 8UL 670 #define SRSS_PWR_CTL2_RET_REG_DIS_Msk 0x100UL 671 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Pos 12UL 672 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Msk 0x1000UL 673 #define SRSS_PWR_CTL2_REFV_DIS_Pos 16UL 674 #define SRSS_PWR_CTL2_REFV_DIS_Msk 0x10000UL 675 #define SRSS_PWR_CTL2_REFV_OK_Pos 17UL 676 #define SRSS_PWR_CTL2_REFV_OK_Msk 0x20000UL 677 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos 20UL 678 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk 0x100000UL 679 #define SRSS_PWR_CTL2_REFVBUF_OK_Pos 21UL 680 #define SRSS_PWR_CTL2_REFVBUF_OK_Msk 0x200000UL 681 #define SRSS_PWR_CTL2_REFVBUF_LPMODE_Pos 22UL 682 #define SRSS_PWR_CTL2_REFVBUF_LPMODE_Msk 0x400000UL 683 #define SRSS_PWR_CTL2_REFI_DIS_Pos 24UL 684 #define SRSS_PWR_CTL2_REFI_DIS_Msk 0x1000000UL 685 #define SRSS_PWR_CTL2_REFI_OK_Pos 25UL 686 #define SRSS_PWR_CTL2_REFI_OK_Msk 0x2000000UL 687 #define SRSS_PWR_CTL2_REFI_LPMODE_Pos 26UL 688 #define SRSS_PWR_CTL2_REFI_LPMODE_Msk 0x4000000UL 689 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos 27UL 690 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk 0x8000000UL 691 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos 28UL 692 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk 0x10000000UL 693 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Pos 31UL 694 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Msk 0x80000000UL 695 /* SRSS.PWR_HIBERNATE */ 696 #define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL 697 #define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 698 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL 699 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 700 #define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL 701 #define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 702 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 703 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 704 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 705 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 706 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 707 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 708 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 709 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 710 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Pos 29UL 711 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Msk 0x20000000UL 712 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 713 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 714 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL 715 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 716 /* SRSS.PWR_BUCK_CTL */ 717 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 718 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 719 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 720 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 721 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 722 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 723 /* SRSS.PWR_BUCK_CTL2 */ 724 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 725 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 726 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 727 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 728 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 729 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 730 /* SRSS.PWR_SSV_CTL */ 731 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos 0UL 732 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk 0x1UL 733 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 3UL 734 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 0x8UL 735 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos 4UL 736 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk 0x10UL 737 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos 6UL 738 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk 0xC0UL 739 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 8UL 740 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 0x100UL 741 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 11UL 742 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 0x800UL 743 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 16UL 744 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 0x10000UL 745 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 19UL 746 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 0x80000UL 747 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 20UL 748 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 0x100000UL 749 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 22UL 750 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 0xC00000UL 751 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 24UL 752 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 0x1000000UL 753 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 27UL 754 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 0x8000000UL 755 /* SRSS.PWR_SSV_STATUS */ 756 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos 0UL 757 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk 0x1UL 758 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos 1UL 759 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk 0x2UL 760 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos 2UL 761 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk 0x4UL 762 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos 8UL 763 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk 0x100UL 764 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos 9UL 765 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk 0x200UL 766 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos 10UL 767 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk 0x400UL 768 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Pos 16UL 769 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Msk 0x10000UL 770 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Pos 17UL 771 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Msk 0x20000UL 772 /* SRSS.PWR_LVD_CTL */ 773 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 774 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 775 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 776 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 777 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 778 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 779 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 8UL 780 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 0x1F00UL 781 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 14UL 782 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 0x4000UL 783 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 15UL 784 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 0x8000UL 785 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 16UL 786 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 0x30000UL 787 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos 18UL 788 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk 0x40000UL 789 /* SRSS.PWR_LVD_CTL2 */ 790 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 8UL 791 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 0x1F00UL 792 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 14UL 793 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 0x4000UL 794 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 15UL 795 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 0x8000UL 796 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 16UL 797 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 0x30000UL 798 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 18UL 799 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 0x40000UL 800 /* SRSS.PWR_REGHC_CTL */ 801 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos 0UL 802 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk 0x1UL 803 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 2UL 804 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 0xCUL 805 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos 4UL 806 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk 0x1F0UL 807 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos 10UL 808 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk 0x400UL 809 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Pos 11UL 810 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Msk 0x800UL 811 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Pos 12UL 812 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Msk 0x7000UL 813 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos 16UL 814 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk 0x10000UL 815 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos 17UL 816 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk 0x20000UL 817 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos 18UL 818 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk 0x40000UL 819 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos 19UL 820 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk 0x80000UL 821 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos 20UL 822 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 823 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Pos 30UL 824 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Msk 0x40000000UL 825 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos 31UL 826 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk 0x80000000UL 827 /* SRSS.PWR_REGHC_STATUS */ 828 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos 0UL 829 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk 0x1UL 830 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos 1UL 831 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk 0x2UL 832 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos 2UL 833 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk 0x4UL 834 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Pos 8UL 835 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Msk 0x100UL 836 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Pos 9UL 837 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Msk 0x200UL 838 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos 12UL 839 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk 0x1000UL 840 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos 31UL 841 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk 0x80000000UL 842 /* SRSS.PWR_REGHC_CTL2 */ 843 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos 0UL 844 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 845 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos 31UL 846 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk 0x80000000UL 847 /* SRSS.PWR_REGHC_CTL4 */ 848 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos 30UL 849 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk 0x40000000UL 850 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos 31UL 851 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk 0x80000000UL 852 /* SRSS.PWR_HIB_DATA */ 853 #define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL 854 #define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 855 /* SRSS.PWR_PMIC_CTL */ 856 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Pos 2UL 857 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Msk 0xCUL 858 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Pos 4UL 859 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Msk 0x1F0UL 860 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Pos 10UL 861 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Msk 0x400UL 862 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Pos 15UL 863 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Msk 0x8000UL 864 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Pos 16UL 865 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Msk 0x10000UL 866 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Pos 17UL 867 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Msk 0x20000UL 868 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Pos 18UL 869 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Msk 0x40000UL 870 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Pos 19UL 871 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Msk 0x80000UL 872 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Pos 20UL 873 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 874 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Pos 31UL 875 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Msk 0x80000000UL 876 /* SRSS.PWR_PMIC_STATUS */ 877 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Pos 0UL 878 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Msk 0x1UL 879 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Pos 12UL 880 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Msk 0x1000UL 881 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Pos 31UL 882 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Msk 0x80000000UL 883 /* SRSS.PWR_PMIC_CTL2 */ 884 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Pos 0UL 885 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 886 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Pos 31UL 887 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Msk 0x80000000UL 888 /* SRSS.PWR_PMIC_CTL4 */ 889 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Pos 30UL 890 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Msk 0x40000000UL 891 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Pos 31UL 892 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Msk 0x80000000UL 893 /* SRSS.PWR_HIB_WAKE_CTL */ 894 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Pos 0UL 895 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk 0xFFFFFFUL 896 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Pos 29UL 897 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 898 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Pos 30UL 899 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk 0x40000000UL 900 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Pos 31UL 901 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk 0x80000000UL 902 /* SRSS.PWR_HIB_WAKE_CTL2 */ 903 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Pos 0UL 904 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Msk 0xFFFFFFUL 905 /* SRSS.PWR_HIB_WAKE_CAUSE */ 906 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Pos 0UL 907 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Msk 0xFFFFFFUL 908 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Pos 29UL 909 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 910 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Pos 30UL 911 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Msk 0x40000000UL 912 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Pos 31UL 913 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Msk 0x80000000UL 914 /* SRSS.CLK_PATH_SELECT */ 915 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 916 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 917 /* SRSS.CLK_ROOT_SELECT */ 918 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 919 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 920 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 921 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 922 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos 8UL 923 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk 0x100UL 924 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL 925 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 926 /* SRSS.CLK_SELECT */ 927 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL 928 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x7UL 929 #define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL 930 #define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 931 #define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL 932 #define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 933 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL 934 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 935 /* SRSS.CLK_ILO0_CONFIG */ 936 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 0UL 937 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 0x1UL 938 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Pos 30UL 939 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Msk 0x40000000UL 940 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos 31UL 941 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk 0x80000000UL 942 /* SRSS.CLK_ILO1_CONFIG */ 943 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Pos 30UL 944 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Msk 0x40000000UL 945 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos 31UL 946 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk 0x80000000UL 947 /* SRSS.CLK_IMO_CONFIG */ 948 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL 949 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 950 /* SRSS.CLK_ECO_CONFIG */ 951 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 952 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 953 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 27UL 954 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 0x8000000UL 955 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 28UL 956 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 0x10000000UL 957 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 958 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 959 /* SRSS.CLK_ECO_PRESCALE */ 960 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 0UL 961 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 0x1UL 962 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 8UL 963 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 0xFF00UL 964 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 16UL 965 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 0x3FF0000UL 966 /* SRSS.CLK_ECO_STATUS */ 967 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL 968 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 969 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL 970 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 971 /* SRSS.CLK_PILO_CONFIG */ 972 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL 973 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL 974 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL 975 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL 976 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL 977 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL 978 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 979 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 980 /* SRSS.CLK_FLL_CONFIG */ 981 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 982 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 983 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 984 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 985 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 986 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 987 /* SRSS.CLK_FLL_CONFIG2 */ 988 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 989 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 990 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 991 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0xFF0000UL 992 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Pos 24UL 993 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Msk 0xFF000000UL 994 /* SRSS.CLK_FLL_CONFIG3 */ 995 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 996 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 997 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 998 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 999 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 1000 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 1001 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 1002 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 1003 /* SRSS.CLK_FLL_CONFIG4 */ 1004 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 1005 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 1006 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 1007 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 1008 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 1009 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 1010 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 1011 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 1012 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 1013 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 1014 /* SRSS.CLK_FLL_STATUS */ 1015 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL 1016 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 1017 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1018 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1019 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL 1020 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 1021 /* SRSS.CLK_ECO_CONFIG2 */ 1022 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos 0UL 1023 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk 0x7UL 1024 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos 4UL 1025 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk 0xF0UL 1026 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos 8UL 1027 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk 0x300UL 1028 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos 10UL 1029 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk 0xC00UL 1030 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos 12UL 1031 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk 0x7000UL 1032 /* SRSS.CLK_PLL_CONFIG */ 1033 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 1034 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 1035 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 1036 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 1037 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 1038 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 1039 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Pos 25UL 1040 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Msk 0x6000000UL 1041 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 1042 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 1043 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 1044 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 1045 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL 1046 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 1047 /* SRSS.CLK_PLL_STATUS */ 1048 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL 1049 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 1050 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1051 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1052 /* SRSS.CSV_REF_SEL */ 1053 #define SRSS_CSV_REF_SEL_REF_MUX_Pos 0UL 1054 #define SRSS_CSV_REF_SEL_REF_MUX_Msk 0x7UL 1055 /* SRSS.RES_CAUSE */ 1056 #define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL 1057 #define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL 1058 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 1059 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 1060 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 1061 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 1062 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Pos 3UL 1063 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Msk 0x8UL 1064 #define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL 1065 #define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL 1066 #define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL 1067 #define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 1068 #define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL 1069 #define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 1070 #define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL 1071 #define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 1072 #define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL 1073 #define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 1074 #define SRSS_RES_CAUSE_RESET_XRES_Pos 16UL 1075 #define SRSS_RES_CAUSE_RESET_XRES_Msk 0x10000UL 1076 #define SRSS_RES_CAUSE_RESET_BODVDDD_Pos 17UL 1077 #define SRSS_RES_CAUSE_RESET_BODVDDD_Msk 0x20000UL 1078 #define SRSS_RES_CAUSE_RESET_BODVDDA_Pos 18UL 1079 #define SRSS_RES_CAUSE_RESET_BODVDDA_Msk 0x40000UL 1080 #define SRSS_RES_CAUSE_RESET_BODVCCD_Pos 19UL 1081 #define SRSS_RES_CAUSE_RESET_BODVCCD_Msk 0x80000UL 1082 #define SRSS_RES_CAUSE_RESET_OVDVDDD_Pos 20UL 1083 #define SRSS_RES_CAUSE_RESET_OVDVDDD_Msk 0x100000UL 1084 #define SRSS_RES_CAUSE_RESET_OVDVDDA_Pos 21UL 1085 #define SRSS_RES_CAUSE_RESET_OVDVDDA_Msk 0x200000UL 1086 #define SRSS_RES_CAUSE_RESET_OVDVCCD_Pos 22UL 1087 #define SRSS_RES_CAUSE_RESET_OVDVCCD_Msk 0x400000UL 1088 #define SRSS_RES_CAUSE_RESET_OCD_ACT_LINREG_Pos 23UL 1089 #define SRSS_RES_CAUSE_RESET_OCD_ACT_LINREG_Msk 0x800000UL 1090 #define SRSS_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Pos 24UL 1091 #define SRSS_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Msk 0x1000000UL 1092 #define SRSS_RES_CAUSE_RESET_OCD_REGHC_Pos 25UL 1093 #define SRSS_RES_CAUSE_RESET_OCD_REGHC_Msk 0x2000000UL 1094 #define SRSS_RES_CAUSE_RESET_PMIC_Pos 26UL 1095 #define SRSS_RES_CAUSE_RESET_PMIC_Msk 0x4000000UL 1096 #define SRSS_RES_CAUSE_RESET_PXRES_Pos 28UL 1097 #define SRSS_RES_CAUSE_RESET_PXRES_Msk 0x10000000UL 1098 #define SRSS_RES_CAUSE_RESET_STRUCT_XRES_Pos 29UL 1099 #define SRSS_RES_CAUSE_RESET_STRUCT_XRES_Msk 0x20000000UL 1100 #define SRSS_RES_CAUSE_RESET_PORVDDD_Pos 30UL 1101 #define SRSS_RES_CAUSE_RESET_PORVDDD_Msk 0x40000000UL 1102 /* SRSS.RES_CAUSE2 */ 1103 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos 0UL 1104 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk 0xFFFFUL 1105 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos 16UL 1106 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk 0x10000UL 1107 /* SRSS.CLK_TRIM_ILO0_CTL */ 1108 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Pos 0UL 1109 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Msk 0x3FUL 1110 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Pos 8UL 1111 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Msk 0xF00UL 1112 /* SRSS.PWR_TRIM_PWRSYS_CTL */ 1113 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL 1114 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL 1115 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL 1116 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL 1117 /* SRSS.CLK_TRIM_PILO_CTL */ 1118 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL 1119 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL 1120 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL 1121 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL 1122 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL 1123 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL 1124 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL 1125 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL 1126 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL 1127 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL 1128 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL 1129 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL 1130 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL 1131 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL 1132 /* SRSS.CLK_TRIM_PILO_CTL2 */ 1133 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL 1134 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL 1135 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL 1136 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL 1137 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL 1138 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL 1139 /* SRSS.CLK_TRIM_PILO_CTL3 */ 1140 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL 1141 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL 1142 /* SRSS.CLK_TRIM_ILO1_CTL */ 1143 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Pos 0UL 1144 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Msk 0x3FUL 1145 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Pos 8UL 1146 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Msk 0xF00UL 1147 1148 1149 #endif /* _CYIP_SRSS_V3_3_H_ */ 1150 1151 1152 /* [] END OF FILE */ 1153
