1 /***************************************************************************//** 2 * \file cyip_lpcomp_v2.h 3 * 4 * \brief 5 * LPCOMP IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_LPCOMP_V2_H_ 28 #define _CYIP_LPCOMP_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * LPCOMP 34 *******************************************************************************/ 35 36 #define LPCOMP_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Low Power Comparators (LPCOMP) 40 */ 41 typedef struct { 42 __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ 43 __IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */ 44 __IM uint32_t RESERVED[2]; 45 __IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */ 46 __IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */ 47 __IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */ 48 __IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */ 49 __IM uint32_t RESERVED1[8]; 50 __IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */ 51 __IM uint32_t RESERVED2[3]; 52 __IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */ 53 __IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */ 54 __IM uint32_t RESERVED3[10]; 55 __IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */ 56 __IM uint32_t RESERVED4[3]; 57 __IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */ 58 __IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */ 59 } LPCOMP_Type; /*!< Size = 152 (0x98) */ 60 61 62 /* LPCOMP.CONFIG */ 63 #define LPCOMP_CONFIG_LPREF_EN_Pos 30UL 64 #define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL 65 #define LPCOMP_CONFIG_ENABLED_Pos 31UL 66 #define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL 67 /* LPCOMP.STATUS */ 68 #define LPCOMP_STATUS_OUT0_Pos 0UL 69 #define LPCOMP_STATUS_OUT0_Msk 0x1UL 70 #define LPCOMP_STATUS_OUT1_Pos 16UL 71 #define LPCOMP_STATUS_OUT1_Msk 0x10000UL 72 /* LPCOMP.INTR */ 73 #define LPCOMP_INTR_COMP0_Pos 0UL 74 #define LPCOMP_INTR_COMP0_Msk 0x1UL 75 #define LPCOMP_INTR_COMP1_Pos 1UL 76 #define LPCOMP_INTR_COMP1_Msk 0x2UL 77 /* LPCOMP.INTR_SET */ 78 #define LPCOMP_INTR_SET_COMP0_Pos 0UL 79 #define LPCOMP_INTR_SET_COMP0_Msk 0x1UL 80 #define LPCOMP_INTR_SET_COMP1_Pos 1UL 81 #define LPCOMP_INTR_SET_COMP1_Msk 0x2UL 82 /* LPCOMP.INTR_MASK */ 83 #define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL 84 #define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL 85 #define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL 86 #define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL 87 /* LPCOMP.INTR_MASKED */ 88 #define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL 89 #define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL 90 #define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL 91 #define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL 92 /* LPCOMP.CMP0_CTRL */ 93 #define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL 94 #define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL 95 #define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL 96 #define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL 97 #define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL 98 #define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL 99 #define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL 100 #define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL 101 #define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL 102 #define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL 103 /* LPCOMP.CMP0_SW */ 104 #define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL 105 #define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL 106 #define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL 107 #define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL 108 #define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL 109 #define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL 110 #define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL 111 #define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL 112 #define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL 113 #define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL 114 #define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL 115 #define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL 116 #define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL 117 #define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL 118 /* LPCOMP.CMP0_SW_CLEAR */ 119 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL 120 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL 121 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL 122 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL 123 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL 124 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL 125 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL 126 #define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL 127 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL 128 #define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL 129 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL 130 #define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL 131 #define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL 132 #define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL 133 /* LPCOMP.CMP1_CTRL */ 134 #define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL 135 #define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL 136 #define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL 137 #define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL 138 #define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL 139 #define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL 140 #define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL 141 #define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL 142 #define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL 143 #define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL 144 /* LPCOMP.CMP1_SW */ 145 #define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL 146 #define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL 147 #define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL 148 #define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL 149 #define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL 150 #define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL 151 #define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL 152 #define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL 153 #define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL 154 #define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL 155 #define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL 156 #define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL 157 #define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL 158 #define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL 159 /* LPCOMP.CMP1_SW_CLEAR */ 160 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL 161 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL 162 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL 163 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL 164 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL 165 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL 166 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL 167 #define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL 168 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL 169 #define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL 170 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL 171 #define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL 172 #define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL 173 #define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL 174 175 176 #endif /* _CYIP_LPCOMP_V2_H_ */ 177 178 179 /* [] END OF FILE */ 180
