34 /* PLL Frequency Auto-Calibration Control 0 Register */
44 /* PLL Frequency Auto-Calibration Control 2 Register */
92 	 * This load operation will ensure PLL setting is taken into  in chip_pll_ctrl()
121 	 * PLL frequency setting = 4 (48MHz)
122 	 * MCU   div = 0 (PLL / 1 = 48 mhz)
123 	 * FND   div = 0 (PLL / 1 = 48 mhz)
124 	 * USB   div = 0 (PLL / 1 = 48 mhz)
125 	 * UART  div = 1 (PLL / 2 = 24 mhz)
126 	 * SMB   div = 1 (PLL / 2 = 24 mhz)
127 	 * SSPI  div = 1 (PLL / 2 = 24 mhz)
129 	 * JTAG  div = 1 (PLL / 2 = 24 mhz)
130 	 * PWM   div = 0 (PLL / 1 = 48 mhz)
131 	 * USBPD div = 5 (PLL / 6 =  8 mhz)
149 	 * PLL frequency setting = 7 (96MHz)
150 	 * MCU   div = 1 (PLL / 2 = 48 mhz)
151 	 * FND   div = 1 (PLL / 2 = 48 mhz)
152 	 * USB   div = 1 (PLL / 2 = 48 mhz)
153 	 * UART  div = 3 (PLL / 4 = 24 mhz)
154 	 * SMB   div = 3 (PLL / 4 = 24 mhz)
155 	 * SSPI  div = 3 (PLL / 4 = 24 mhz)
157 	 * JTAG  div = 3 (PLL / 4 = 24 mhz)
158 	 * PWM   div = 1 (PLL / 2 = 48 mhz)
159 	 * USBPD div = 11 (PLL / 12 =  8 mhz)
178 void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll)  in chip_run_pll_sequence()  argument
183 	 * Configure PLL clock dividers.  in chip_run_pll_sequence()
185 	 * PLL frequency immediately until the status is changed  in chip_run_pll_sequence()
189 	 * complete PLL update.  in chip_run_pll_sequence()
191 	IT8XXX2_ECPM_PLLFREQR = pll->pll_freq;  in chip_run_pll_sequence()
192 	/* Pre-set FND clock frequency = PLL / 3 */  in chip_run_pll_sequence()
195 	IT8XXX2_ECPM_SCDCR3 = (pll->div_jtag << 4) | pll->div_ec;  in chip_run_pll_sequence()
201 	IT8XXX2_ECPM_SCDCR0 = (pll->div_fnd << 4) | pll->div_mcu;  in chip_run_pll_sequence()
205 	IT8XXX2_ECPM_SCDCR1 = (pll->div_usb << 4) | pll->div_uart;  in chip_run_pll_sequence()
207 	IT8XXX2_ECPM_SCDCR2 = (pll->div_sspi << 4) | pll->div_smb;  in chip_run_pll_sequence()
209 	IT8XXX2_ECPM_SCDCR4 = (pll->div_usbpd << 4) | pll->div_pwm;  in chip_run_pll_sequence()
212 static void chip_configure_pll(const struct pll_config_t *pll)  in chip_configure_pll()  argument
214 	/* Re-configure PLL clock or not. */  in chip_configure_pll()
215 	if (((IT8XXX2_ECPM_PLLFREQR & 0xf) != pll->pll_freq) ||  in chip_configure_pll()
216 		((IT8XXX2_ECPM_SCDCR0 & 0xf0) != (pll->div_fnd << 4)) ||  in chip_configure_pll()
217 		((IT8XXX2_ECPM_SCDCR3 & 0xf) != pll->div_ec)) {  in chip_configure_pll()
221 		 * PLL sequence or sequence will fail if CS# pin is low.  in chip_configure_pll()
225 		/* Run change PLL sequence */  in chip_configure_pll()
226 		chip_run_pll_sequence(pll);  in chip_configure_pll()
228 		/* Enable eSPI pad after changing PLL sequence */  in chip_configure_pll()
241 	/* Disable auto calibration before setting PLL frequency */  in chip_change_pll()
246 	/* configure PLL/CPU/flash clock */  in chip_change_pll()