Lines Matching +full:stm32 +full:- +full:rcc
2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
21 zephyr,flash-controller = &flash;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,cortex-m33";
33 cpu-power-states = <&stop>;
34 #address-cells = <1>;
35 #size-cells = <1>;
38 compatible = "arm,armv8m-mpu";
45 clk_hse: clk-hse {
46 #clock-cells = <0>;
47 compatible = "st,stm32-hse-clock";
51 clk_hsi: clk-hsi {
52 #clock-cells = <0>;
53 compatible = "st,stm32h7-hsi-clock";
54 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
55 clock-frequency = <DT_FREQ_M(64)>;
59 clk_hsi48: clk-hsi48 {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <DT_FREQ_M(48)>;
66 clk_csi: clk-csi {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <DT_FREQ_M(4)>;
73 clk_lse: clk-lse {
74 #clock-cells = <0>;
75 compatible = "st,stm32-lse-clock";
76 clock-frequency = <32768>;
77 driving-capability = <2>;
81 clk_lsi: clk-lsi {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <DT_FREQ_K(32)>;
89 #clock-cells = <0>;
90 compatible = "st,stm32u5-pll-clock";
95 #clock-cells = <0>;
96 compatible = "st,stm32u5-pll-clock";
103 compatible = "st,stm32-clock-mco";
108 compatible = "st,stm32-clock-mco";
114 flash: flash-controller@40022000 {
115 compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
119 #address-cells = <1>;
120 #size-cells = <1>;
123 compatible = "st,stm32-nv-flash", "soc-nv-flash";
125 write-block-size = <16>;
126 erase-block-size = <8192>;
128 max-erase-time = <5>;
133 compatible = "zephyr,memory-region", "st,stm32-backup-sram";
135 clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
136 zephyr,memory-region = "BACKUP_SRAM";
140 power-states {
142 compatible = "zephyr,power-state";
143 power-state-name = "suspend-to-idle";
144 substate-id = <1>;
145 min-residency-us = <20>;
149 rcc: rcc@44020c00 { label
150 compatible = "st,stm32u5-rcc";
151 clocks-controller;
152 #clock-cells = <2>;
155 rctl: reset-controller {
156 compatible = "st,stm32-rcc-rctl";
157 #reset-cells = <1>;
161 exti: interrupt-controller@44022000 {
162 compatible = "st,stm32g0-exti", "st,stm32-exti";
163 interrupt-controller;
164 #interrupt-cells = <1>;
165 #address-cells = <1>;
167 num-lines = <16>;
172 interrupt-names = "line0", "line1", "line2", "line3",
176 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
182 pinctrl: pin-controller@42020000 {
183 compatible = "st,stm32-pinctrl";
184 #address-cells = <1>;
185 #size-cells = <1>;
189 compatible = "st,stm32-gpio";
190 gpio-controller;
191 #gpio-cells = <2>;
193 clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
197 compatible = "st,stm32-gpio";
198 gpio-controller;
199 #gpio-cells = <2>;
201 clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
205 compatible = "st,stm32-gpio";
206 gpio-controller;
207 #gpio-cells = <2>;
209 clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
213 compatible = "st,stm32-gpio";
214 gpio-controller;
215 #gpio-cells = <2>;
217 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
221 compatible = "st,stm32-gpio";
222 gpio-controller;
223 #gpio-cells = <2>;
225 clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
230 compatible = "st,stm32-lptim";
231 clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
232 #address-cells = <1>;
233 #size-cells = <0>;
236 interrupt-names = "wakeup";
241 compatible = "st,stm32-lptim";
242 clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
243 #address-cells = <1>;
244 #size-cells = <0>;
247 interrupt-names = "wakeup";
252 compatible = "st,stm32-usart", "st,stm32-uart";
254 clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
261 compatible = "st,stm32-usart", "st,stm32-uart";
263 clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
270 compatible = "st,stm32-usart", "st,stm32-uart";
272 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
279 compatible = "st,stm32-lpuart", "st,stm32-uart";
281 clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
288 compatible = "st,stm32-watchdog";
294 compatible = "st,stm32-window-watchdog";
296 clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
302 compatible = "st,stm32-dac";
304 clocks = <&rcc STM32_CLOCK(AHB2, 11U)>;
306 #io-channel-cells = <1>;
310 compatible = "st,stm32-adc";
312 clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
315 vref-mv = <3300>;
316 #io-channel-cells = <1>;
321 sampling-times = <3 7 13 25 48 93 248 641>;
322 st,adc-sequencer = "FULLY_CONFIGURABLE";
323 st,adc-oversampler = "OVERSAMPLER_MINIMAL";
327 compatible = "st,stm32-rtc";
330 clocks = <&rcc STM32_CLOCK(APB3, 21U)>;
332 alarms-count = <2>;
333 alrm-exti-line = <17>;
338 compatible = "st,stm32-timers";
340 clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
343 interrupt-names = "brk", "up", "trgcom", "cc";
347 compatible = "st,stm32-pwm";
349 #pwm-cells = <3>;
354 compatible = "st,stm32-timers";
356 clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
359 interrupt-names = "global";
363 compatible = "st,stm32-pwm";
365 #pwm-cells = <3>;
369 compatible = "st,stm32-counter";
375 compatible = "st,stm32-timers";
377 clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
380 interrupt-names = "global";
384 compatible = "st,stm32-pwm";
386 #pwm-cells = <3>;
390 compatible = "st,stm32-counter";
396 compatible = "st,stm32-timers";
398 clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
401 interrupt-names = "global";
405 compatible = "st,stm32-pwm";
407 #pwm-cells = <3>;
411 compatible = "st,stm32-counter";
417 compatible = "st,stm32-timers";
419 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
422 interrupt-names = "global";
426 compatible = "st,stm32-pwm";
428 #pwm-cells = <3>;
432 compatible = "st,stm32-counter";
438 compatible = "st,stm32-i2c-v2";
439 clock-frequency = <I2C_BITRATE_STANDARD>;
440 #address-cells = <1>;
441 #size-cells = <0>;
443 clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
445 interrupt-names = "event", "error";
450 compatible = "st,stm32-i2c-v2";
451 clock-frequency = <I2C_BITRATE_STANDARD>;
452 #address-cells = <1>;
453 #size-cells = <0>;
455 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
457 interrupt-names = "event", "error";
462 compatible = "st,stm32-i3c";
465 interrupt-names = "event", "error";
466 #address-cells = <3>;
467 #size-cells = <0>;
468 clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
470 zephyr,pm-device-runtime-auto;
475 compatible = "st,stm32-i3c";
478 interrupt-names = "event", "error";
479 #address-cells = <3>;
480 #size-cells = <0>;
481 clocks = <&rcc STM32_CLOCK(APB3, 9U)>;
483 zephyr,pm-device-runtime-auto;
488 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
489 #address-cells = <1>;
490 #size-cells = <0>;
493 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
494 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
499 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
500 #address-cells = <1>;
501 #size-cells = <0>;
504 clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
505 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
510 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
511 #address-cells = <1>;
512 #size-cells = <0>;
515 clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
516 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
521 compatible = "st,stm32-fdcan";
523 reg-names = "m_can", "message_ram";
525 interrupt-names = "int0", "int1";
526 clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
527 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
532 compatible = "st,stm32-rng";
534 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
536 nist-config = <0xf00d00>;
537 health-test-config = <0xaac7>;
542 compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
545 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
546 clocks = <&rcc STM32_CLOCK(AHB1, 19U)>,
547 <&rcc STM32_CLOCK(AHB1, 20U)>,
548 <&rcc STM32_CLOCK(AHB1, 21U)>;
552 compatible = "st,stm32-mdio";
553 #address-cells = <1>;
554 #size-cells = <0>;
560 compatible = "st,stm32u5-dma";
561 #dma-cells = <3>;
564 clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
565 dma-channels = <8>;
566 dma-requests = <140>;
567 dma-offset = <0>;
572 compatible = "st,stm32u5-dma";
573 #dma-cells = <3>;
576 clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
577 dma-channels = <8>;
578 dma-requests = <140>;
579 dma-offset = <8>;
584 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
585 #address-cells = <1>;
586 #size-cells = <0>;
588 clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
589 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
594 dma-names = "tx", "rx";
600 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
601 #address-cells = <1>;
602 #size-cells = <0>;
604 clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
605 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
610 dma-names = "tx", "rx";
616 compatible = "st,stm32h7-i2s", "st,stm32-i2s";
617 #address-cells = <1>;
618 #size-cells = <0>;
620 clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
621 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
626 dma-names = "tx", "rx";
632 compatible = "st,stm32-usb";
635 interrupt-names = "usb";
636 num-bidir-endpoints = <8>;
637 ram-size = <2048>;
639 clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
640 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
645 compatible = "st,stm32-digi-temp";
648 interrupt-names = "digi_temp";
649 clocks = <&rcc STM32_CLOCK(APB1_2, 3U)>;
655 compatible = "st,stm32-temp-cal";
656 ts-cal1-addr = <0x08fff814>;
657 ts-cal2-addr = <0x08fff818>;
658 ts-cal1-temp = <30>;
659 ts-cal2-temp = <130>;
660 ts-cal-vrefanalog = <3300>;
661 ts-cal-resolution = <12>;
662 io-channels = <&adc1 16>;
667 compatible = "st,stm32-vref";
668 vrefint-cal-addr = <0x08FFF810>;
669 vrefint-cal-mv = <3300>;
670 io-channels = <&adc1 17>;
675 compatible = "st,stm32-vbat";
677 io-channels = <&adc1 2>;
682 compatible = "usb-nop-xceiv";
683 #phy-cells = <0>;
687 compatible = "st,stm32-smbus";
688 #address-cells = <1>;
689 #size-cells = <0>;
695 compatible = "st,stm32-smbus";
696 #address-cells = <1>;
697 #size-cells = <0>;
704 arm,num-irq-priority-bits = <4>;