Lines Matching +full:sampling +full:- +full:times

4  * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
14 			compatible = "st,stm32f411-plli2s-clock";
19 		compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
22 			compatible = "st,stm32-i2s";
23 			#address-cells = <1>;
24 			#size-cells = <0>;
30 			dma-names = "tx", "rx";
35 			compatible = "st,stm32-usart", "st,stm32-uart";
44 			compatible ="st,stm32-uart";
53 			compatible = "st,stm32-uart";
62 			compatible = "st,stm32-bxcan";
65 			interrupt-names = "TX", "RX0", "RX1", "SCE";
71 			compatible = "st,stm32-bxcan";
74 			interrupt-names = "TX", "RX0", "RX1", "SCE";
77 			master-can-reg = <0x40006400>;
82 			num-bidir-endpoints = <6>;
88 			compatible = "st,stm32-otghs";
91 			interrupt-names = "otghs", "ep1_out", "ep1_in";
92 			num-bidir-endpoints = <9>;
93 			ram-size = <4096>;
94 			maximum-speed = "full-speed";
102 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
105 			zephyr,memory-region = "BACKUP_SRAM";
110 			compatible = "st,stm32-adc";
115 			#io-channel-cells = <1>;
120 			sampling-times = <3 15 28 56 84 112 144 480>;
121 			st,adc-clock-source = "SYNC";
122 			st,adc-sequencer = "FULLY_CONFIGURABLE";
123 			st,adc-oversampler = "OVERSAMPLER_NONE";
127 			compatible = "st,stm32-adc";
132 			#io-channel-cells = <1>;
137 			sampling-times = <3 15 28 56 84 112 144 480>;
138 			st,adc-clock-source = "SYNC";
139 			st,adc-sequencer = "FULLY_CONFIGURABLE";
140 			st,adc-oversampler = "OVERSAMPLER_NONE";
144 			compatible = "st,stm32-dac";
148 			#io-channel-cells = <1>;
151 		fmc: memory-controller@a0000000 {
152 			compatible = "st,stm32-fmc";
158 				compatible = "st,stm32-fmc-sdram";
159 				#address-cells = <1>;
160 				#size-cells = <0>;
167 		io-channels = <&adc1 18>;
171 		compatible = "usb-nop-xceiv";
172 		#phy-cells = <0>;