Lines Matching +full:0 +full:x44610000
15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
27 reg = <0xe000ed90 0x40>;
38 reg = <0x44611000 0x80>;
46 mboxes = <&mu5 0>;
50 #size-cells = <0>;
54 reg = <0x14>;
60 reg = <0x19>;
70 itcm: itcm@0 {
72 reg = <0x0 DT_SIZE_K(256)>;
77 reg = <0x20000000 DT_SIZE_K(256)>;
82 reg = <0x42000000 (DT_SIZE_K(64) * 33)>;
84 interrupts = <143 0>, <143 0>;
91 reg = <0x424e0000 0x88>;
92 interrupts = <73 0>;
101 reg = <0x424f0000 0x88>;
102 interrupts = <74 0>;
111 reg = <0x42500000 0x88>;
112 interrupts = <75 0>;
121 reg = <0x42510000 0x88>;
122 interrupts = <76 0>;
133 #size-cells = <0>;
134 reg = <0x42530000 0x4000>;
135 interrupts = <58 0>;
144 #size-cells = <0>;
145 reg = <0x42540000 0x4000>;
146 interrupts = <59 0>;
153 reg = <0x42570000 DT_SIZE_K(64)>;
161 reg = <0x42580000 DT_SIZE_K(64)>;
169 reg = <0x42590000 DT_SIZE_K(64)>;
177 reg = <0x425a0000 DT_SIZE_K(64)>;
185 reg = <0x42650000 DT_SIZE_K(64)>;
188 interrupts = <170 0>;
198 reg = <0x42690000 DT_SIZE_K(64)>;
206 reg = <0x426a0000 DT_SIZE_K(64)>;
216 #size-cells = <0>;
217 reg = <0x426b0000 0x4000>;
218 interrupts = <181 0>;
227 #size-cells = <0>;
228 reg = <0x426c0000 0x4000>;
229 interrupts = <182 0>;
238 #size-cells = <0>;
239 reg = <0x426d0000 0x4000>;
240 interrupts = <183 0>;
249 #size-cells = <0>;
250 reg = <0x426e0000 0x4000>;
251 interrupts = <184 0>;
258 reg = <0x44310000 0x88>;
259 interrupts = <29 0>;
268 reg = <0x44320000 0x88>;
269 interrupts = <30 0>;
280 #size-cells = <0>;
281 reg = <0x44340000 0x4000>;
282 interrupts = <13 0>;
291 #size-cells = <0>;
292 reg = <0x44350000 0x4000>;
293 interrupts = <14 0>;
300 reg = <0x44380000 DT_SIZE_K(64)>;
308 reg = <0x44390000 DT_SIZE_K(64)>;
316 reg = <0x44610000 DT_SIZE_K(4)>;
317 interrupts = <205 0>;