122 static inline void mss_spi_write(const struct mss_spi_config *cfg, mm_reg_t offset, uint32_t val)  in mss_spi_write()  function
131 	mss_spi_write(cfg, MSS_SPI_REG_FRAMESUP, (len & MSS_SPI_FRAMESUP_UP_BYTES_MSK));  in mss_spi_hw_tfsz_set()
135 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_hw_tfsz_set()
144 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_enable_controller()
153 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_disable_controller()
164 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_enable_ints()
176 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_disable_ints()
215 				mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, data8);  in mss_spi_readwr_fifo()
218 				mss_spi_write(cfg, MSS_SPI_REG_TX_DATA, 0x0);  in mss_spi_readwr_fifo()
233 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_select_slave()
243 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_activate_cs()
251 	mss_spi_write(cfg, MSS_SPI_REG_SS, reg);  in mss_spi_deactivate_cs()
271 	mss_spi_write(cfg, MSS_SPI_REG_CLK_GEN, val);  in mss_spi_clk_gen_set()
293 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_hw_mode_set()
309 	mss_spi_write(cfg, MSS_SPI_REG_INT_CLEAR, intfield);  in mss_spi_interrupt()
357 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, xfer->control);  in mss_spi_configure()
365 	mss_spi_write(cfg, MSS_SPI_REG_TXRXDF_SIZE, MSS_SPI_FRAMESIZE_DEFAULT);  in mss_spi_configure()
367 	mss_spi_write(cfg, MSS_SPI_REG_COMMAND, MSS_SPI_COMMAND_FIFO_MASK);  in mss_spi_configure()
432 	mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control);  in mss_spi_init()