124 int enabled_clock(uint32_t src_clk)  in enabled_clock()  argument
126 	if ((src_clk == STM32_SRC_SYSCLK) ||  in enabled_clock()
127 	    (src_clk == STM32_SRC_HCLK) ||  in enabled_clock()
128 	    (src_clk == STM32_SRC_PCLK1) ||  in enabled_clock()
129 	    (src_clk == STM32_SRC_PCLK2) ||  in enabled_clock()
130 	    (src_clk == STM32_SRC_PCLK3) ||  in enabled_clock()
131 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||  in enabled_clock()
132 	    ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||  in enabled_clock()
133 	    ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||  in enabled_clock()
134 	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||  in enabled_clock()
135 	    ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||  in enabled_clock()
136 	    ((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) ||  in enabled_clock()
137 	    ((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED)) ||  in enabled_clock()
138 	    ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||  in enabled_clock()
139 	    ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||  in enabled_clock()
140 	    ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||  in enabled_clock()
141 	    ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||  in enabled_clock()
142 	    ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||  in enabled_clock()
143 	    ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||  in enabled_clock()
144 	    ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||  in enabled_clock()
145 	    ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||  in enabled_clock()
146 	    ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {  in enabled_clock()