57 	if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
58 	    (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
59 	    (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
61 	} else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
62 		   (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
63 		   (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
65 	} else if ((IS_ENABLED(STM32_PLL_SRC_MSIS) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
66 		   (IS_ENABLED(STM32_PLL2_SRC_MSIS) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
67 		   (IS_ENABLED(STM32_PLL3_SRC_MSIS) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
131 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||  in enabled_clock()
132 	    ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||  in enabled_clock()
133 	    ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||  in enabled_clock()
134 	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||  in enabled_clock()
135 	    ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||  in enabled_clock()
136 	    ((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) ||  in enabled_clock()
137 	    ((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED)) ||  in enabled_clock()
138 	    ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||  in enabled_clock()
139 	    ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||  in enabled_clock()
140 	    ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||  in enabled_clock()
141 	    ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||  in enabled_clock()
142 	    ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||  in enabled_clock()
143 	    ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||  in enabled_clock()
144 	    ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||  in enabled_clock()
145 	    ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||  in enabled_clock()
146 	    ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {  in enabled_clock()
466 		if (IS_ENABLED(STM32_PLL_SRC_MSIS)) {  in set_epod_booster()
469 		} else if (IS_ENABLED(STM32_PLL_SRC_HSE) && (MHZ(16) < STM32_HSE_FREQ)) {  in set_epod_booster()
532 	if (IS_ENABLED(STM32_PLL_SRC_HSE)) {  in set_up_plls()
535 	} else if (IS_ENABLED(STM32_PLL_SRC_MSIS)) {  in set_up_plls()
538 	} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {  in set_up_plls()
565 	if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {  in set_up_plls()
570 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {  in set_up_plls()
575 	if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {  in set_up_plls()
580 	if (IS_ENABLED(STM32_PLL_R_ENABLED)) {  in set_up_plls()
597 	if (IS_ENABLED(STM32_PLL2_SRC_HSE)) {  in set_up_plls()
599 	} else if (IS_ENABLED(STM32_PLL2_SRC_MSIS)) {  in set_up_plls()
601 	} else if (IS_ENABLED(STM32_PLL2_SRC_HSI)) {  in set_up_plls()
619 	if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {  in set_up_plls()
624 	if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {  in set_up_plls()
629 	if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {  in set_up_plls()
634 	if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {  in set_up_plls()
649 	if (IS_ENABLED(STM32_PLL3_SRC_HSE)) {  in set_up_plls()
651 	} else if (IS_ENABLED(STM32_PLL3_SRC_MSIS)) {  in set_up_plls()
653 	} else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) {  in set_up_plls()
671 	if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {  in set_up_plls()
676 	if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {  in set_up_plls()
681 	if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {  in set_up_plls()
686 	if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {  in set_up_plls()
705 	if (IS_ENABLED(STM32_HSE_ENABLED)) {  in set_up_fixed_clock_sources()
707 		if (IS_ENABLED(STM32_HSE_BYPASS)) {  in set_up_fixed_clock_sources()
720 	if (IS_ENABLED(STM32_HSI_ENABLED)) {  in set_up_fixed_clock_sources()
731 	if (IS_ENABLED(STM32_LSE_ENABLED)) {  in set_up_fixed_clock_sources()
746 		if (IS_ENABLED(STM32_LSE_BYPASS)) {  in set_up_fixed_clock_sources()
766 	if (IS_ENABLED(STM32_MSIS_ENABLED)) {  in set_up_fixed_clock_sources()
772 		if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {  in set_up_fixed_clock_sources()
788 	if (IS_ENABLED(STM32_MSIK_ENABLED)) {  in set_up_fixed_clock_sources()
794 		if (IS_ENABLED(STM32_MSIK_PLL_MODE)) {  in set_up_fixed_clock_sources()
802 		if (IS_ENABLED(STM32_MSIS_ENABLED)) {  in set_up_fixed_clock_sources()
815 	if (IS_ENABLED(STM32_LSI_ENABLED)) {  in set_up_fixed_clock_sources()
837 	if (IS_ENABLED(STM32_HSI48_ENABLED)) {  in set_up_fixed_clock_sources()
878 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_init()
883 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {  in stm32_clock_control_init()
888 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_MSIS)) {  in stm32_clock_control_init()
893 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {  in stm32_clock_control_init()