1                     Microsoft's Azure RTOS ThreadX for Cortex-M0
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3             Using ARM Compiler 5 (AC5) and Keil Microcontroller Development Kit
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51.  Building the ThreadX run-time Library
6
7Building the ThreadX library is easy, simply load the project file
8tx.uvprojx, which is located inside the "example_build" directory.
9
10Once the ThreadX library files are displayed in the project window,
11select the "Build Target" operation and observe the compilation and assembly
12of the ThreadX library. This project build produces the ThreadX library
13file tx.lib.
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15
162.  Demonstration System
17
18The ThreadX demonstration is designed to execute under the Keil simulator or
19Cortex-M0 hardware. This demonstration is slightly smaller than typical ThreadX
20demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM.
21
22Building the demonstration is easy; simply open the ThreadX demonstration
23project file sample_threadx.uvprojx, which is located inside the "example_build"
24directory.
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26Once open, select the "Build Target" operation and observe the compilation of
27sample_threadx.c (which is the demonstration application) and linking with
28tx.lib. The resulting file sample_threadx.axf is a binary file that can be downloaded
29and executed under the uVision simulator or Cortex-M0 hardware.
30
31For simulator execution, the following memory regions need to be defined via
32the "Debug -> Memory Map" dialog:
33
340x20000000, 0x20080000 [check read and write access]
350xE0000000, 0xE8000000 [check read and write access]
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37
383.  System Initialization
39
40The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label
41__main. This is defined within the AC5 compiler's startup code. In
42addition, this is where all static and global pre-set C variable
43initialization processing takes place.
44
45The ThreadX tx_initialize_low_level.s file is responsible for setting up
46various system data structures, the vector area, and a periodic timer interrupt
47source.
48
49In addition, _tx_initialize_low_level determines the first available
50address for use by the application, which is supplied as the sole input
51parameter to your application definition function, tx_application_define.
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53
544.  Register Usage and Stack Frames
55
56The following defines the saved context stack frames for context switches
57that occur as a result of interrupt handling or from thread-level API calls.
58All suspended threads have the same stack frame in the Cortex-M0 version of
59ThreadX. The top of the suspended thread's stack is pointed to by
60tx_thread_stack_ptr in the associated thread control block TX_THREAD.
61
62
63  Stack Offset     Stack Contents
64
65     0x00               r8
66     0x04               r9
67     0x08               r10
68     0x0C               r11
69     0x10               r4
70     0x14               r5
71     0x18               r6
72     0x1C               r7
73     0x20               r0          (Hardware stack starts here!!)
74     0x24               r1
75     0x28               r2
76     0x2C               r3
77     0x30               r12
78     0x34               lr
79     0x38               pc
80     0x3C               xPSR
81
82
835.  Improving Performance
84
85The distribution version of ThreadX is built without any compiler
86optimizations. This makes it easy to debug because you can trace or set
87breakpoints inside of ThreadX itself. Of course, this costs some
88performance. To make it run faster, you can change the build_threadx.bat file to
89remove the -g option and enable all compiler optimizations.
90
91In addition, you can eliminate the ThreadX basic API error checking by
92compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
93defined.
94
95
966.  Interrupt Handling
97
98ThreadX provides complete and high-performance interrupt handling for Cortex-M0
99targets. There are a certain set of requirements that are defined in the
100following sub-sections:
101
102
1036.1  Vector Area
104
105The Cortex-M0 vectors start at the label __tx_vectors. The application may modify
106the vector area according to its needs.
107
1086.2 Managed Interrupts
109
110ISRs for Cortex-M can be written completely in C (or assembly language) without any
111calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
112access to the ThreadX API that is available to ISRs.
113
114ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
115
116void    your_C_isr(void)
117{
118
119    /* ISR processing goes here, including any needed function calls.  */
120}
121
122ISRs written in assembly language will take the form:
123
124    EXPORT  your_assembly_isr
125your_assembly_isr
126
127    PUSH    {r0, lr}
128
129    ; ISR processing goes here, including any needed function calls.
130
131    POP     {r0, r1}
132    MOV     lr, r1
133    BX      lr
134
135
1367.  Revision History
137
138For generic code revision information, please refer to the readme_threadx_generic.txt
139file, which is included in your distribution. The following details the revision
140information associated with this specific port of ThreadX:
141
14204-02-2021  Release 6.1.6 changes:
143            tx_port.h                           Updated macro definition
144            tx_thread_schedule.s                Fix compilation error
145
14603-02-2021  The following files were changed/added for version 6.1.5:
147            tx_thread_schedule.s            Added low power feature
148
14909-30-2020  Initial ThreadX 6.1 version for Cortex-M0 using Keil tools.
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151
152Copyright(c) 1996-2020 Microsoft Corporation
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154
155https://azure.com/rtos
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