1                     Microsoft's Azure RTOS ThreadX for Cortex-M0
2
3                             Using ARM Compiler 6 & DS
4
51. Import the ThreadX Projects
6
7In order to build the ThreadX library and the ThreadX demonstration, first import
8the 'tx' and 'sample_threadx' projects (located in the "example_build" directory)
9into your DS workspace.
10
11
122.  Building the ThreadX run-time Library
13
14Building the ThreadX library is easy; simply right-click the Eclipse project
15"tx" and then select the "Build Project" button. You should now observe the compilation
16and assembly of the ThreadX library. This project build produces the ThreadX
17library file tx.a.
18
19
203.  Demonstration System
21
22The ThreadX demonstration is designed to execute under the DS debugger on the
23MPS2_Cortex_M0 Bare Metal simulator.
24
25Building the demonstration is easy; simply right-click the Eclipse project
26"sample_threadx" and then select the "Build Project" button. You should now observe
27the compilation and assembly of the ThreadX demonstration. This project build produces
28the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder
29in the Project Explorer window, right-click on the 'cortex-m0_tx.launch' file, click
30'Debug As', and then click 'cortex-m0_tx' from the submenu. This will cause the
31debugger to load the sample_threadx.axf ELF file and run to main. You are now ready
32to execute the ThreadX demonstration.
33
34
354.  System Initialization
36
37The entry point in ThreadX for the Cortex-M0 using AC6 tools uses the standard AC6
38Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized.
39
40The ThreadX tx_initialize_low_level.S file is responsible for setting up
41various system data structures, the vector area, and a periodic timer interrupt
42source.
43
44In addition, _tx_initialize_low_level determines the first available
45address for use by the application, which is supplied as the sole input
46parameter to your application definition function, tx_application_define.
47
48
495.  Register Usage and Stack Frames
50
51The following defines the saved context stack frames for context switches
52that occur as a result of interrupt handling or from thread-level API calls.
53All suspended threads have the same stack frame in the Cortex-M0 version of
54ThreadX. The top of the suspended thread's stack is pointed to by
55tx_thread_stack_ptr in the associated thread control block TX_THREAD.
56
57
58  Stack Offset     Stack Contents
59
60     0x00               r8
61     0x04               r9
62     0x08               r10
63     0x0C               r11
64     0x10               r4
65     0x14               r5
66     0x18               r6
67     0x1C               r7
68     0x20               r0          (Hardware stack starts here!!)
69     0x24               r1
70     0x28               r2
71     0x2C               r3
72     0x30               r12
73     0x34               lr
74     0x38               pc
75     0x3C               xPSR
76
77
786.  Improving Performance
79
80The distribution version of ThreadX is built without any compiler optimizations.
81This makes it easy to debug because you can trace or set breakpoints inside of
82ThreadX itself. Of course, this costs some performance. To make it run faster,
83you can change the build_threadx.bat file to remove the -g option and enable
84all compiler optimizations.
85
86In addition, you can eliminate the ThreadX basic API error checking by
87compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
88defined.
89
90
917.  Interrupt Handling
92
93ThreadX provides complete and high-performance interrupt handling for Cortex-M0
94targets. There are a certain set of requirements that are defined in the
95following sub-sections:
96
97
987.1  Vector Area
99
100The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify
101the vector area according to its needs. There is code in tx_initialize_low_level() that will
102configure the vector base register.
103
104
1057.2 Managed Interrupts
106
107ISRs can be written completely in C (or assembly language) without any calls to
108_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
109ThreadX API that is available to ISRs.
110
111ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
112
113void    your_C_isr(void)
114{
115
116    /* ISR processing goes here, including any needed function calls.  */
117}
118
119ISRs written in assembly language will take the form:
120
121
122        .global  your_assembly_isr
123        .thumb_func
124your_assembly_isr:
125; VOID your_assembly_isr(VOID)
126; {
127        PUSH    {r0, lr}
128;
129;    /* Do interrupt handler work here */
130;    /* BL <your interrupt routine in C> */
131
132        POP     {r0, r1}
133        MOV     lr, r1
134        BX      lr
135; }
136
137
138Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set.
139To accomplish this, the declaration of the label has to be preceded by the assembler directive
140.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to
141be inserted in the correct location in the interrupt vector table. This table is typically
142located in either your runtime startup file or in the tx_initialize_low_level.S file.
143
144
1458.  Revision History
146
147For generic code revision information, please refer to the readme_threadx_generic.txt
148file, which is included in your distribution. The following details the revision
149information associated with this specific port of ThreadX:
150
15104-02-2021  Release 6.1.6 changes:
152            tx_port.h                           Updated macro definition
153
15403-02-2021  The following files were changed/added for version 6.1.5:
155            tx_thread_schedule.s            Added low power feature
156
15709-30-2020  Initial ThreadX 6.1 version for Cortex-M0 using AC6 tools.
158
159
160Copyright(c) 1996-2020 Microsoft Corporation
161
162
163https://azure.com/rtos
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165