1 Microsoft's Azure RTOS ThreadX for Cortex-M55 2 3 Using the IAR Tools 4 5 61. Building the ThreadX run-time Library 7 8Import all ThreadX common and port-specific source files into an IAR project. 9Configure the project to build a library rather than an executable. This 10results in the ThreadX run-time library file tx.a, which is needed by 11the application. 12Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 13replace the common files of the same name. 14 152. Demonstration System 16 17No demonstration is provided because the IAR EWARM 8.50 simulator does 18not simulate the Cortex-M55 correctly. 19 20 213. System Initialization 22 23The entry point in ThreadX for the Cortex-M55 using IAR tools is at label 24__iar_program_start. This is defined within the IAR compiler's startup code. 25In addition, this is where all static and global preset C variable 26initialization processing takes place. 27 28The ThreadX tx_initialize_low_level.s file is responsible for setting up 29various system data structures, and a periodic timer interrupt source. 30 31The _tx_initialize_low_level function inside of tx_initialize_low_level.s 32also determines the first available address for use by the application, which 33is supplied as the sole input parameter to your application definition function, 34tx_application_define. To accomplish this, a section is created in 35tx_initialize_low_level.s called FREE_MEM, which must be located after all 36other RAM sections in memory. 37 38 394. Register Usage and Stack Frames 40 41The following defines the saved context stack frames for context switches 42that occur as a result of interrupt handling or from thread-level API calls. 43All suspended threads have the same stack frame in the Cortex-M55 version of 44ThreadX. The top of the suspended thread's stack is pointed to by 45tx_thread_stack_ptr in the associated thread control block TX_THREAD. 46 47Non-FPU Stack Frame: 48 49 Stack Offset Stack Contents 50 51 0x00 LR Interrupted LR (LR at time of PENDSV) 52 0x04 r4 Software stacked GP registers 53 0x08 r5 54 0x0C r6 55 0x10 r7 56 0x14 r8 57 0x18 r9 58 0x1C r10 59 0x20 r11 60 0x24 r0 Hardware stacked registers 61 0x28 r1 62 0x2C r2 63 0x30 r3 64 0x34 r12 65 0x38 lr 66 0x3C pc 67 0x40 xPSR 68 69FPU Stack Frame (only interrupted thread with FPU enabled): 70 71 Stack Offset Stack Contents 72 73 0x00 LR Interrupted LR (LR at time of PENDSV) 74 0x04 s16 Software stacked FPU registers 75 0x08 s17 76 0x0C s18 77 0x10 s19 78 0x14 s20 79 0x18 s21 80 0x1C s22 81 0x20 s23 82 0x24 s24 83 0x28 s25 84 0x2C s26 85 0x30 s27 86 0x34 s28 87 0x38 s29 88 0x3C s30 89 0x40 s31 90 0x44 r4 Software stacked registers 91 0x48 r5 92 0x4C r6 93 0x50 r7 94 0x54 r8 95 0x58 r9 96 0x5C r10 97 0x60 r11 98 0x64 r0 Hardware stacked registers 99 0x68 r1 100 0x6C r2 101 0x70 r3 102 0x74 r12 103 0x78 lr 104 0x7C pc 105 0x80 xPSR 106 0x84 s0 Hardware stacked FPU registers 107 0x88 s1 108 0x8C s2 109 0x90 s3 110 0x94 s4 111 0x98 s5 112 0x9C s6 113 0xA0 s7 114 0xA4 s8 115 0xA8 s9 116 0xAC s10 117 0xB0 s11 118 0xB4 s12 119 0xB8 s13 120 0xBC s14 121 0xC0 s15 122 0xC4 fpscr 123 124 1255. Improving Performance 126 127To make ThreadX and the application(s) run faster, you can enable 128all compiler optimizations. 129 130In addition, you can eliminate the ThreadX basic API error checking by 131compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 132defined. 133 134 1356. Interrupt Handling 136 137The Cortex-M55 vectors start at the label __vector_table and is typically defined in a 138startup.s file (or similar). The application may modify the vector area according to its needs. 139 140 1416.1 Managed Interrupts 142 143ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly 144language) without any calls to _tx_thread_context_save or _tx_thread_context_restore. 145These ISRs are allowed access to the ThreadX API that is available to ISRs. 146 147ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): 148 149void your_C_isr(void) 150{ 151 152 /* ISR processing goes here, including any needed function calls. */ 153} 154 155ISRs written in assembly language will take the form: 156 157 PUBLIC your_assembly_isr 158your_assembly_isr: 159 160 PUSH {r0, lr} 161 162 ; ISR processing goes here, including any needed function calls. 163 164 POP {r0, lr} 165 BX lr 166 167 1687. IAR Thread-safe Library Support 169 170Thread-safe support for the IAR tools is easily enabled by building the ThreadX library 171and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file 172should have the following line added (if not already in place): 173 174initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application 175 176 1777. IAR Thread-safe Library Support 178 179Thread-safe support for the IAR tools is easily enabled by building the ThreadX library 180and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file 181should have the following line added (if not already in place): 182 183initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application 184 185The project options "General Options -> Library Configuration" should also have the 186"Enable thread support in library" box selected. 187 188 1898. VFP Support 190 191ThreadX for Cortex-M55 supports automatic ("lazy") VFP support, which means that applications threads 192can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 193context. 194 195 1969. Revision History 197 198For generic code revision information, please refer to the readme_threadx_generic.txt 199file, which is included in your distribution. The following details the revision 200information associated with this specific port of ThreadX: 201 20206-02-2021 Release 6.1.7 changes: 203 tx_thread_secure_stack_initialize.s New file 204 tx_thread_schedule.s Added secure stack initialize to SVC hander 205 tx_thread_secure_stack.c Fixed stack pointer save, initialize in handler mode 206 20704-02-2021 Release 6.1.6 changes: 208 tx_port.h Updated macro definition 209 tx_thread_schedule.s Added low power support 210 21103-02-2021 The following files were changed/added for version 6.1.5: 212 tx_port.h Added ULONG64_DEFINED 213 21409-30-2020 Initial ThreadX 6.1 version for Cortex-M55 using IAR's ARM tools. 215 216 217Copyright(c) 1996-2020 Microsoft Corporation 218 219 220https://azure.com/rtos 221 222
