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/ThreadX-v6.4.1/ports/arc_hs/metaware/src/
Dtx_thread_register_bank_assign.s89 ld r5, [r4, 164] ; Pickup initial status32 from stack area
91 st r5, [r4, 164] ; Store initial status32 in stack area
/ThreadX-v6.4.1/ports/c667x/ccs/src/
Dtx_thread_stack_build.asm161 LDW *+A4(16),A0 ; Pickup end of stack area
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/example_build/
Dtx_initialize_low_level.S96 LDR r0, =_end @ Get end of non-initialized RAM area
/ThreadX-v6.4.1/ports_module/cortex_r4/iar/module_manager/src/
Dtxm_module_manager_thread_stack_build.s101 LDR r2, [r0, #16] ; Pickup end of stack area
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/example_build/
Dtx_initialize_low_level.s96 LDR r0, =_end @ Get end of non-initialized RAM area
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/
Dtxm_module_manager_thread_stack_build.s111 LDR r2, [r0, #16] ; Pickup end of stack area
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_initialize_low_level.s93 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/
Dtx_initialize_low_level.s93 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
Dtx_initialize_low_level.s93 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
/ThreadX-v6.4.1/utility/rtos_compatibility_layers/OSEK/
Dtx_osek.c746 ULONG area; in ActivateTask() local
755 area = osek_task_independent_area(); in ActivateTask()
756 if(area != TX_TRUE) in ActivateTask()
904 ULONG area; in TerminateTask() local
913 area = osek_task_independent_area(); in TerminateTask()
914 if(area != TX_TRUE) in TerminateTask()
1080 ULONG area; in ChainTask() local
1087 area = osek_task_independent_area(); in ChainTask()
1088 if(area != TX_TRUE) in ChainTask()
1347 ULONG area; in GetTaskState() local
[all …]
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtxm_module_manager_thread_stack_build.s113 LDR r2, [r0, #16] ; Pickup end of stack area
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/
Dreadme_threadx.txt40 various system data structures, the vector area, and a periodic timer interrupt
41 source. By default, the vector area is defined to be located in the Init area,
42 which is defined at the top of tx_initialize_low_level.s. This area is typically
44 of the Init area should be copied to address 0.
115 Init area contains the vectors and is loaded at address zero. On actual
116 hardware platforms, this area might have to be copied to address 0.
/ThreadX-v6.4.1/ports/cortex_m4/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-M4 vector area. */
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/example_build/
Dtx_initialize_low_level.S119 LDR r1, =_end @ Get end of non-initialized RAM area
/ThreadX-v6.4.1/ports/cortex_m3/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-M3 vector area. */
Dsample_threadx_el.ld12 # sdabase - base of the small data area section pointer
/ThreadX-v6.4.1/ports/cortex_m7/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-M7 vector area. */
/ThreadX-v6.4.1/ports/cortex_r4/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-R4 vector area. This should be located or copied to 0. */
/ThreadX-v6.4.1/ports/cortex_r5/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-R5 vector area. This should be located or copied to 0. */
/ThreadX-v6.4.1/ports/cortex_a8/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-A8 vector area. This should be located or copied to 0. */
/ThreadX-v6.4.1/ports/cortex_a5/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-A5 vector area. This should be located or copied to 0. */
/ThreadX-v6.4.1/ports/cortex_a9/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-A9 vector area. This should be located or copied to 0. */
Dsample_threadx_el.ld12 # sdabase - base of the small data area section pointer
/ThreadX-v6.4.1/ports/cortex_r7/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-R7 vector area. This should be located or copied to 0. */
/ThreadX-v6.4.1/ports/cortex_a7/ghs/example_build/
Dreset.arm3 #/* Define the Cortex-A7 vector area. This should be located or copied to 0. */

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