1;/*************************************************************************** 2; * Copyright (c) 2024 Microsoft Corporation 3; * 4; * This program and the accompanying materials are made available under the 5; * terms of the MIT License which is available at 6; * https://opensource.org/licenses/MIT. 7; * 8; * SPDX-License-Identifier: MIT 9; **************************************************************************/ 10; 11; 12;/**************************************************************************/ 13;/**************************************************************************/ 14;/** */ 15;/** ThreadX Component */ 16;/** */ 17;/** Thread */ 18;/** */ 19;/**************************************************************************/ 20;/**************************************************************************/ 21; 22; 23;#define TX_SOURCE_CODE 24; 25; 26;/* Include necessary system files. */ 27; 28;#include "tx_api.h" 29;#include "tx_thread.h" 30; 31FP .set A15 32DP .set B14 33SP .set B15 34ADDRESS_MSK .set 0xFFFFFFF0 35; 36 .sect ".text" 37;/**************************************************************************/ 38;/* */ 39;/* FUNCTION RELEASE */ 40;/* */ 41;/* _tx_thread_stack_build C667x/TI */ 42;/* 6.1 */ 43;/* AUTHOR */ 44;/* */ 45;/* William E. Lamie, Microsoft Corporation */ 46;/* */ 47;/* DESCRIPTION */ 48;/* */ 49;/* This function builds a stack frame on the supplied thread's stack. */ 50;/* The stack frame results in a fake interrupt return to the supplied */ 51;/* function pointer. */ 52;/* */ 53;/* INPUT */ 54;/* */ 55;/* thread_ptr Pointer to thread control blk */ 56;/* function_ptr Pointer to return function */ 57;/* */ 58;/* OUTPUT */ 59;/* */ 60;/* None */ 61;/* */ 62;/* CALLS */ 63;/* */ 64;/* None */ 65;/* */ 66;/* CALLED BY */ 67;/* */ 68;/* _tx_thread_create Create thread service */ 69;/* */ 70;/* RELEASE HISTORY */ 71;/* */ 72;/* DATE NAME DESCRIPTION */ 73;/* */ 74;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 75;/* */ 76;/**************************************************************************/ 77;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) 78;{ 79 .global _tx_thread_stack_build 80_tx_thread_stack_build: 81; 82; 83; /* Build a fake interrupt frame. The form of the fake interrupt stack 84; on the C667x should look like the following after it is built: 85; 86; Stack Top: N/A Available for use 87; 1 Interrupt stack frame type 4 88; CSR Initial value for CSR 8 89; IRP Initial thread entry 12 90; AMR Initial thread addressing mode 16 91; A0 Initial A0 20 92; A1 Initial A1 24 93; A2 Initial A2 28 94; A3 Initial A3 32 95; A4 Initial A4 36 96; A5 Initial A5 40 97; A6 Initial A6 44 98; A7 Initial A7 48 99; A8 Initial A8 52 100; A9 Initial A9 56 101; A10 Initial A10 60 102; A11 Initial A11 64 103; A12 Initial A12 68 104; A13 Initial A13 72 105; A14 Initial A14 76 106; A15 (FP) Initial A15 (FP) 80 107; B0 Initial B0 84 108; B1 Initial B1 88 109; B2 Initial B2 92 110; B3 Initial B3 96 111; B4 Initial B4 100 112; B5 Initial B5 104 113; B6 Initial B6 108 114; B7 Initial B7 112 115; B8 Initial B8 116 116; B9 Initial B9 120 117; B10 Initial B10 124 118; B11 Initial B11 128 119; B12 Initial B12 132 120; B13 Initial B13 136 121; A16 Initial A16 140 122; A17 Initial A17 144 123; A18 Initial A18 148 124; A19 Initial A19 152 125; A20 Initial A20 156 126; A21 Initial A21 160 127; A22 Initial A22 164 128; A23 Initial A23 168 129; A24 Initial A24 172 130; A25 Initial A25 176 131; A26 Initial A26 180 132; A27 Initial A27 184 133; A28 Initial A28 188 134; A29 Initial A29 192 135; A30 Initial A30 196 136; A31 Initial A31 200 137; B16 Initial B16 204 138; B17 Initial B17 208 139; B18 Initial B18 212 140; B19 Initial B19 216 141; B20 Initial B20 220 142; B21 Initial B21 224 143; B22 Initial B22 228 144; B23 Initial B23 232 145; B24 Initial B24 236 146; B25 Initial B25 240 147; B26 Initial B26 244 148; B27 Initial B27 248 149; B28 Initial B28 252 150; B29 Initial B29 256 151; B30 Initial B30 260 152; B31 Initial B31 264 153; ILC Initial ILC 268 154; RILC Initial RILC 272 155; ITSR Initial ITSR 276 156 157 158; 159; Stack Bottom: (higher memory address) */ 160; 161 LDW *+A4(16),A0 ; Pickup end of stack area 162 MVKL ADDRESS_MSK,A1 ; Build address mask 163 MVKH ADDRESS_MSK,A1 ; 164 MVC CSR,B0 ; Pickup current CSR 165 AND -2,B0,B0 ; Clear GIE bit 166 OR 2,B0,B0 ; Set PGIE bit for interrupt return 167 AND A1,A0,A0 ; Ensure alignment 168 MVKL 288,A2 ; Calculate stack size 169 SUB A0,A2,A0 ; Allocate space on thread's stack 170; 171; /* Actually build the stack frame. */ 172; 173 MVKL 1,A2 ; Build stack type 174 ZERO A3 ; Clear value 175 STW A2,*+A0(4) ; Interrupt stack type 176 STW B0,*+A0(8) ; Initial CSR 177 STW B4,*+A0(12) ; Thread shell entry point 178 STW A3,*+A0(16) ; Initial AMR 179 STW A3,*+A0(20) ; Initial A0 180 STW A3,*+A0(24) ; Initial A1 181 STW A3,*+A0(28) ; Initial A2 182 STW A3,*+A0(32) ; Initial A3 183 STW A3,*+A0(36) ; Initial A4 184 STW A3,*+A0(40) ; Initial A5 185 STW A3,*+A0(44) ; Initial A6 186 STW A3,*+A0(48) ; Initial A7 187 STW A3,*+A0(52) ; Initial A8 188 STW A3,*+A0(56) ; Initial A9 189 STW A3,*+A0(60) ; Initial A10 190 STW A3,*+A0(64) ; Initial A11 191 STW A3,*+A0(68) ; Initial A12 192 STW A3,*+A0(72) ; Initial A13 193 STW A3,*+A0(76) ; Initial A14 194 STW A3,*+A0(80) ; Initial A15 195 STW A3,*+A0(84) ; Initial B0 196 STW A3,*+A0(88) ; Initial B1 197 STW A3,*+A0(92) ; Initial B2 198 STW A3,*+A0(96) ; Initial B3 199 STW A3,*+A0(100) ; Initial B4 200 STW A3,*+A0(104) ; Initial B5 201 STW A3,*+A0(108) ; Initial B6 202 STW A3,*+A0(112) ; Initial B7 203 STW A3,*+A0(116) ; Initial B8 204 STW A3,*+A0(120) ; Initial B9 205 STW A3,*+A0(124) ; Initial B10 206 MVKL 128,A2 ; Stack adjustment value 207 ADD A2,A0,A2 ; Adjust pointer into stack frame 208 STW A3,*+A2(0) ; Initial B11 209 STW A3,*+A2(4) ; Initial B12 210 STW A3,*+A2(8) ; Initial B13 211 STW A3,*+A2(12) ; Initial A16 212 STW A3,*+A2(16) ; Initial A17 213 STW A3,*+A2(20) ; Initial A18 214 STW A3,*+A2(24) ; Initial A19 215 STW A3,*+A2(28) ; Initial A20 216 STW A3,*+A2(32) ; Initial A21 217 STW A3,*+A2(36) ; Initial A22 218 STW A3,*+A2(40) ; Initial A23 219 STW A3,*+A2(44) ; Initial A24 220 STW A3,*+A2(48) ; Initial A25 221 STW A3,*+A2(52) ; Initial A26 222 STW A3,*+A2(56) ; Initial A27 223 STW A3,*+A2(60) ; Initial A28 224 STW A3,*+A2(64) ; Initial A29 225 STW A3,*+A2(68) ; Initial A30 226 STW A3,*+A2(72) ; Initial A31 227 STW A3,*+A2(76) ; Initial B16 228 STW A3,*+A2(80) ; Initial B17 229 STW A3,*+A2(84) ; Initial B18 230 STW A3,*+A2(88) ; Initial B19 231 STW A3,*+A2(92) ; Initial B20 232 STW A3,*+A2(96) ; Initial B21 233 STW A3,*+A2(100) ; Initial B22 234 STW A3,*+A2(104) ; Initial B23 235 STW A3,*+A2(108) ; Initial B24 236 STW A3,*+A2(112) ; Initial B25 237 STW A3,*+A2(116) ; Initial B26 238 STW A3,*+A2(120) ; Initial B27 239 STW A3,*+A2(124) ; Initial B28 240 ADDK 128,A2 ; Adjust stack pointer again 241 STW A3,*+A2(0) ; Initial B29 242 STW A3,*+A2(4) ; Initial B30 243 STW A3,*+A2(8) ; Initial B31 244 B B3 ; Return to caller 245 STW A3,*+A2(12) ; Initial ILC 246 STW A3,*+A2(16) ; Initial RILC 247 MVKL 0x3,B0 ; Build initial ITSR (set GIE and SGIE bits) 248 STW B0,*+A2(20) ; Store ITSR 249; 250; /* Setup stack pointer. */ 251; thread_ptr -> tx_thread_stack_ptr = A0; 252; 253 STW A0,*+A4(8) ; Save stack pointer in thread's 254 ; control block 255;} 256 257
