Searched refs:DVFS (Results 1 – 25 of 26) sorted by relevance
12
8 - ti,enable-pwm-dvfs: Enable the DVFS voltage control through the PWM interface.9 - ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this10 will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage
18 the PM functions which include clock/DVFS/thermal/power from the CPU.
40 enum bd9571mwv_regulators { VD09, VD18, VD25, VD33, DVFS }; enumerator142 BD9571MWV_REG("DVFS", "dvfs", DVFS, reg_ops,
838 with Serial VID control and DVFS.
22 For power management (particularly DVFS and AVS), the North Bridge
61 - The voltage and frequency levels as a result of DVFS. The DVFS
2 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"7 devfreq, a generic DVFS framework can be registered for a device
199 * however both the Armbian DVFS table and the official one201 * DVFS table are known to work properly at the lowest
408 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
647 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
751 /* DVFS */
72 switch their DVFS state together, i.e. they share clock/voltage/current lines.173 Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.227 Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states280 * Missing opp-shared property means CPUs switch DVFS states308 DVFS state together.
54 firmware providing the CPU DVFS functionality.72 Say Y, if you have a Broadcom SoC with AVS support for DFS or DVFS.239 firmware providing the CPU DVFS functionality.
33 Dynamic Voltage and Frequency Scaling (DVFS)
16 firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
4 The i.MX6 General Power Control (GPC) block contains DVFS load tracking
6 voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
229 access SDRAM during CORE DVFS, select Y here. This should boost
139 (online + offline) CPUs that do DVFS259 particular order, but if they are cpufreq core will do DVFS a bit
40 to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
19 It should be a DCF interrupt. When DDR DVFS finishes
47 frequency scaling (DVFS), and uses lower frequencies as cooling states.202 * Here is an example of describing a cooling device for a DVFS
69 power states, various power domain DVFS including the core/cluster,
182 This will throttle the device by limiting the maximum allowed DVFS
251 attribute is useful for user space DVFS controllers to get better
