1* Rockchip rk3399 DMC (Dynamic Memory Controller) device
2
3Required properties:
4- compatible:		 Must be "rockchip,rk3399-dmc".
5- devfreq-events:	 Node to get DDR loading, Refer to
6			 Documentation/devicetree/bindings/devfreq/event/
7			 rockchip-dfi.txt
8- clocks:		 Phandles for clock specified in "clock-names" property
9- clock-names :		 The name of clock used by the DFI, must be
10			 "pclk_ddr_mon";
11- operating-points-v2:	 Refer to Documentation/devicetree/bindings/opp/opp.txt
12			 for details.
13- center-supply:	 DMC supply node.
14- status:		 Marks the node enabled/disabled.
15
16Optional properties:
17- interrupts:		 The CPU interrupt number. The interrupt specifier
18			 format depends on the interrupt controller.
19			 It should be a DCF interrupt. When DDR DVFS finishes
20			 a DCF interrupt is triggered.
21
22Following properties relate to DDR timing:
23
24- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/rk3399-ddr.h,
25				  it selects the DDR3 cl-trp-trcd type. It must be
26				  set according to "Speed Bin" in DDR3 datasheet,
27				  DO NOT use a smaller "Speed Bin" than specified
28				  for the DDR3 being used.
29
30- rockchip,pd_idle :		  Configure the PD_IDLE value. Defines the
31				  power-down idle period in which memories are
32				  placed into power-down mode if bus is idle
33				  for PD_IDLE DFI clock cycles.
34
35- rockchip,sr_idle :		  Configure the SR_IDLE value. Defines the
36				  self-refresh idle period in which memories are
37				  placed into self-refresh mode if bus is idle
38				  for SR_IDLE * 1024 DFI clock cycles (DFI
39				  clocks freq is half of DRAM clock), default
40				  value is "0".
41
42- rockchip,sr_mc_gate_idle :	  Defines the memory self-refresh and controller
43				  clock gating idle period. Memories are placed
44				  into self-refresh mode and memory controller
45				  clock arg gating started if bus is idle for
46				  sr_mc_gate_idle*1024 DFI clock cycles.
47
48- rockchip,srpd_lite_idle :	  Defines the self-refresh power down idle
49				  period in which memories are placed into
50				  self-refresh power down mode if bus is idle
51				  for srpd_lite_idle * 1024 DFI clock cycles.
52				  This parameter is for LPDDR4 only.
53
54- rockchip,standby_idle :	  Defines the standby idle period in which
55				  memories are placed into self-refresh mode.
56				  The controller, pi, PHY and DRAM clock will
57				  be gated if bus is idle for standby_idle * DFI
58				  clock cycles.
59
60- rockchip,dram_dll_dis_freq :	  Defines the DDR3 DLL bypass frequency in MHz.
61				  When DDR frequency is less than DRAM_DLL_DISB_FREQ,
62				  DDR3 DLL will be bypassed. Note: if DLL was bypassed,
63				  the odt will also stop working.
64
65- rockchip,phy_dll_dis_freq :	  Defines the PHY dll bypass frequency in
66				  MHz (Mega Hz). When DDR frequency is less than
67				  DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
68				  Note: PHY DLL and PHY ODT are independent.
69
70- rockchip,ddr3_odt_dis_freq :	  When the DRAM type is DDR3, this parameter defines
71				  the ODT disable frequency in MHz (Mega Hz).
72				  when the DDR frequency is  less then ddr3_odt_dis_freq,
73				  the ODT on the DRAM side and controller side are
74				  both disabled.
75
76- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines
77				  the DRAM side driver strength in ohms. Default
78				  value is DDR3_DS_40ohm.
79
80- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines
81				  the DRAM side ODT strength in ohms. Default value
82				  is DDR3_ODT_120ohm.
83
84- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines
85				  the phy side CA line (incluing command line,
86				  address line and clock line) driver strength.
87				  Default value is PHY_DRV_ODT_40.
88
89- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines
90				  the PHY side DQ line (including DQS/DQ/DM line)
91				  driver strength. Default value is PHY_DRV_ODT_40.
92
93- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines
94				  the PHY side ODT strength. Default value is
95				  PHY_DRV_ODT_240.
96
97- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
98				  then ODT disable frequency in MHz (Mega Hz).
99				  When DDR frequency is less then ddr3_odt_dis_freq,
100				  the ODT on the DRAM side and controller side are
101				  both disabled.
102
103- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines
104				  the DRAM side driver strength in ohms. Default
105				  value is LP3_DS_34ohm.
106
107- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines
108				  the DRAM side ODT strength in ohms. Default value
109				  is LP3_ODT_240ohm.
110
111- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines
112				  the PHY side CA line (including command line,
113				  address line and clock line) driver strength.
114				  Default value is PHY_DRV_ODT_40.
115
116- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines
117				  the PHY side DQ line (including DQS/DQ/DM line)
118				  driver strength. Default value is
119				  PHY_DRV_ODT_40.
120
121- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define
122				  the phy side odt strength, default value is
123				  PHY_DRV_ODT_240.
124
125- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
126				  defines the ODT disable frequency in
127				  MHz (Mega Hz). When the DDR frequency is less then
128				  ddr3_odt_dis_freq, the ODT on the DRAM side and
129				  controller side are both disabled.
130
131- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines
132				  the DRAM side driver strength in ohms. Default
133				  value is LP4_PDDS_60ohm.
134
135- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines
136				  the DRAM side ODT on DQS/DQ line strength in ohms.
137				  Default value is LP4_DQ_ODT_40ohm.
138
139- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines
140				  the DRAM side ODT on CA line strength in ohms.
141				  Default value is LP4_CA_ODT_40ohm.
142
143- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines
144				  the PHY side CA line (including command address
145				  line) driver strength. Default value is
146				  PHY_DRV_ODT_40.
147
148- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
149				  the PHY side clock line and CS line driver
150				  strength. Default value is PHY_DRV_ODT_80.
151
152- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines
153				  the PHY side DQ line (including DQS/DQ/DM line)
154				  driver strength. Default value is PHY_DRV_ODT_80.
155
156- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines
157				  the PHY side ODT strength. Default value is
158				  PHY_DRV_ODT_60.
159
160Example:
161	dmc_opp_table: dmc_opp_table {
162		compatible = "operating-points-v2";
163
164		opp00 {
165			opp-hz = /bits/ 64 <300000000>;
166			opp-microvolt = <900000>;
167		};
168		opp01 {
169			opp-hz = /bits/ 64 <666000000>;
170			opp-microvolt = <900000>;
171		};
172	};
173
174	dmc: dmc {
175		compatible = "rockchip,rk3399-dmc";
176		devfreq-events = <&dfi>;
177		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
178		clocks = <&cru SCLK_DDRCLK>;
179		clock-names = "dmc_clk";
180		operating-points-v2 = <&dmc_opp_table>;
181		center-supply = <&ppvar_centerlogic>;
182		upthreshold = <15>;
183		downdifferential = <10>;
184		rockchip,ddr3_speed_bin = <21>;
185		rockchip,pd_idle = <0x40>;
186		rockchip,sr_idle = <0x2>;
187		rockchip,sr_mc_gate_idle = <0x3>;
188		rockchip,srpd_lite_idle	= <0x4>;
189		rockchip,standby_idle = <0x2000>;
190		rockchip,dram_dll_dis_freq = <300>;
191		rockchip,phy_dll_dis_freq = <125>;
192		rockchip,auto_pd_dis_freq = <666>;
193		rockchip,ddr3_odt_dis_freq = <333>;
194		rockchip,ddr3_drv = <DDR3_DS_40ohm>;
195		rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
196		rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
197		rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
198		rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
199		rockchip,lpddr3_odt_dis_freq = <333>;
200		rockchip,lpddr3_drv = <LP3_DS_34ohm>;
201		rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
202		rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
203		rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
204		rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
205		rockchip,lpddr4_odt_dis_freq = <333>;
206		rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
207		rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
208		rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
209		rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
210		rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
211		rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
212		rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
213	};
214