1Freescale i.MX General Power Controller
2=======================================
3
4The i.MX6 General Power Control (GPC) block contains DVFS load tracking
5counters and Power Gating Control (PGC).
6
7Required properties:
8- compatible: Should be one of the following:
9  - fsl,imx6q-gpc
10  - fsl,imx6qp-gpc
11  - fsl,imx6sl-gpc
12  - fsl,imx6sx-gpc
13- reg: should be register base and length as documented in the
14  datasheet
15- interrupts: Should contain one interrupt specifier for the GPC interrupt
16- clocks: Must contain an entry for each entry in clock-names.
17  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
18- clock-names: Must include the following entries:
19  - ipg
20
21The power domains are generic power domain providers as documented in
22Documentation/devicetree/bindings/power/power_domain.txt. They are described as
23subnodes of the power gating controller 'pgc' node of the GPC and should
24contain the following:
25
26Required properties:
27- reg: Must contain the DOMAIN_INDEX of this power domain
28  The following DOMAIN_INDEX values are valid for i.MX6Q:
29  ARM_DOMAIN     0
30  PU_DOMAIN      1
31  The following additional DOMAIN_INDEX value is valid for i.MX6SL:
32  DISPLAY_DOMAIN 2
33  The following additional DOMAIN_INDEX value is valid for i.MX6SX:
34  PCI_DOMAIN     3
35
36- #power-domain-cells: Should be 0
37
38Optional properties:
39- clocks: a number of phandles to clocks that need to be enabled during domain
40  power-up sequencing to ensure reset propagation into devices located inside
41  this power domain
42- power-supply: a phandle to the regulator powering this domain
43
44Example:
45
46	gpc: gpc@20dc000 {
47		compatible = "fsl,imx6q-gpc";
48		reg = <0x020dc000 0x4000>;
49		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
50			     <0 90 IRQ_TYPE_LEVEL_HIGH>;
51		clocks = <&clks IMX6QDL_CLK_IPG>;
52		clock-names = "ipg";
53
54		pgc {
55			#address-cells = <1>;
56			#size-cells = <0>;
57
58			power-domain@0 {
59				reg = <0>;
60				#power-domain-cells = <0>;
61			};
62
63			pd_pu: power-domain@1 {
64				reg = <1>;
65				#power-domain-cells = <0>;
66				power-supply = <&reg_pu>;
67				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
68				         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
69				         <&clks IMX6QDL_CLK_GPU2D_CORE>,
70				         <&clks IMX6QDL_CLK_GPU2D_AXI>,
71				         <&clks IMX6QDL_CLK_OPENVG_AXI>,
72				         <&clks IMX6QDL_CLK_VPU_AXI>;
73			};
74		};
75	};
76
77
78Specifying power domain for IP modules
79======================================
80
81IP cores belonging to a power domain should contain a 'power-domains' property
82that is a phandle pointing to the power domain the device belongs to.
83
84Example of a device that is part of the PU power domain:
85
86	vpu: vpu@2040000 {
87		reg = <0x02040000 0x3c000>;
88		/* ... */
89		power-domains = <&pd_pu>;
90		/* ... */
91	};
92