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Searched +full:r9a06g032 +full:- +full:sysctrl (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/arch/arm/boot/dts/
Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Drenesas,r9a06g032-sysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1D (R9A06G032) System Controller
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
15 const: renesas,r9a06g032-sysctrl
23 - description: External 40 MHz crystal
24 - description: Optional external 32.768 kHz crystal
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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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/Linux-v5.15/drivers/soc/renesas/
Dr9a06g032-smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R9A06G032 Second CA7 enabler.
8 * Derived from actions,s500-smp
18 * writing an address into the BOOTADDR register of sysctrl.
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus()
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/Linux-v5.15/include/dt-bindings/clock/
Dr9a06g032-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R9A06G032 sysctrl IDs
/Linux-v5.15/drivers/clk/renesas/
Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
3 * R9A06G032 clock driver
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
46 /* For fixed-factor ones */
323 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_set()
334 u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); in clk_rdesc_get()
341 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
342 * clock gate framework as the gates on the R9A06G032 have a special enabling
383 struct device_node *np = dev->of_node; in r9a06g032_attach_dev()
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