Lines Matching +full:r9a06g032 +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
25 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
30 compatible = "arm,cortex-a7";
32 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
33 enable-method = "renesas,r9a06g032-smp";
34 cpu-release-addr = <0 0x4000c204>;
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <40000000>;
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
66 interrupt-parent = <&gic>;
69 sysctrl: system-controller@4000c000 { label
70 compatible = "renesas,r9a06g032-sysctrl";
73 #clock-cells = <1>;
77 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
81 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
84 reg-shift = <2>;
85 reg-io-width = <4>;
86 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
87 clock-names = "baudclk", "apb_pclk";
92 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
95 reg-shift = <2>;
96 reg-io-width = <4>;
97 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
98 clock-names = "baudclk", "apb_pclk";
103 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
106 reg-shift = <2>;
107 reg-io-width = <4>;
108 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
109 clock-names = "baudclk", "apb_pclk";
114 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
120 clock-names = "baudclk", "apb_pclk";
125 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
131 clock-names = "baudclk", "apb_pclk";
136 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
139 reg-shift = <2>;
140 reg-io-width = <4>;
141 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
142 clock-names = "baudclk", "apb_pclk";
147 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
153 clock-names = "baudclk", "apb_pclk";
158 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
161 reg-shift = <2>;
162 reg-io-width = <4>;
163 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
164 clock-names = "baudclk", "apb_pclk";
169 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
171 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
172 clock-names = "bus";
176 gic: interrupt-controller@44101000 {
177 compatible = "arm,gic-400", "arm,cortex-a7-gic";
178 interrupt-controller;
179 #interrupt-cells = <3>;
190 compatible = "arm,cortex-a7-timer",
191 "arm,armv7-timer";
192 interrupt-parent = <&gic>;
193 arm,cpu-registers-not-fw-configured;
194 always-on;