1 // SPDX-License-Identifier: GPL-2.0
3  * R9A06G032 clock driver
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
46 		/* For fixed-factor ones */
323 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));  in clk_rdesc_set()
334 	u32 __iomem *reg = clocks->reg + (4 * (one >> 5));  in clk_rdesc_get()
341  * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
342  * clock gate framework as the gates on the R9A06G032 have a special enabling
383 	struct device_node *np = dev->of_node;  in r9a06g032_attach_dev()
389 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,  in r9a06g032_attach_dev()
391 		if (clkspec.np != pd->dev.of_node)  in r9a06g032_attach_dev()
416 	struct device_node *np = dev->of_node;  in r9a06g032_add_clk_domain()
421 		return -ENOMEM;  in r9a06g032_add_clk_domain()
423 	pd->name = np->name;  in r9a06g032_add_clk_domain()
424 	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in r9a06g032_add_clk_domain()
426 	pd->attach_dev = r9a06g032_attach_dev;  in r9a06g032_add_clk_domain()
427 	pd->detach_dev = r9a06g032_detach_dev;  in r9a06g032_add_clk_domain()
440 	WARN_ON(!g->gate);  in r9a06g032_clk_gate_set()
442 	spin_lock_irqsave(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
443 	clk_rdesc_set(clocks, g->gate, on);  in r9a06g032_clk_gate_set()
444 	/* De-assert reset */  in r9a06g032_clk_gate_set()
445 	if (g->reset)  in r9a06g032_clk_gate_set()
446 		clk_rdesc_set(clocks, g->reset, 1);  in r9a06g032_clk_gate_set()
447 	spin_unlock_irqrestore(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
456 	if (g->ready || g->midle) {  in r9a06g032_clk_gate_set()
457 		spin_lock_irqsave(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
458 		if (g->ready)  in r9a06g032_clk_gate_set()
459 			clk_rdesc_set(clocks, g->ready, on);  in r9a06g032_clk_gate_set()
461 		if (g->midle)  in r9a06g032_clk_gate_set()
462 			clk_rdesc_set(clocks, g->midle, !on);  in r9a06g032_clk_gate_set()
463 		spin_unlock_irqrestore(&clocks->lock, flags);  in r9a06g032_clk_gate_set()
472 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);  in r9a06g032_clk_gate_enable()
480 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);  in r9a06g032_clk_gate_disable()
488 	if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))  in r9a06g032_clk_gate_is_enabled()
491 	return clk_rdesc_get(g->clocks, g->gate.gate);  in r9a06g032_clk_gate_is_enabled()
513 	init.name = desc->name;  in r9a06g032_register_gate()
519 	g->clocks = clocks;  in r9a06g032_register_gate()
520 	g->index = desc->index;  in r9a06g032_register_gate()
521 	g->gate = desc->gate;  in r9a06g032_register_gate()
522 	g->hw.init = &init;  in r9a06g032_register_gate()
529 	if (r9a06g032_clk_gate_is_enabled(&g->hw)) {  in r9a06g032_register_gate()
531 		pr_debug("%s was enabled, making read-only\n", desc->name);  in r9a06g032_register_gate()
534 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_gate()
560 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);  in r9a06g032_div_recalc_rate()
563 	if (div < clk->min)  in r9a06g032_div_recalc_rate()
564 		div = clk->min;  in r9a06g032_div_recalc_rate()
565 	else if (div > clk->max)  in r9a06g032_div_recalc_rate()
566 		div = clk->max;  in r9a06g032_div_recalc_rate()
584 	if (div <= clk->min)  in r9a06g032_div_clamp_div()
585 		return clk->min;  in r9a06g032_div_clamp_div()
586 	if (div >= clk->max)  in r9a06g032_div_clamp_div()
587 		return clk->max;  in r9a06g032_div_clamp_div()
589 	for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {  in r9a06g032_div_clamp_div()
590 		if (div >= clk->table[i] && div <= clk->table[i + 1]) {  in r9a06g032_div_clamp_div()
591 			unsigned long m = rate -  in r9a06g032_div_clamp_div()
592 				DIV_ROUND_UP(prate, clk->table[i]);  in r9a06g032_div_clamp_div()
594 				DIV_ROUND_UP(prate, clk->table[i + 1]) -  in r9a06g032_div_clamp_div()
600 			div = p >= m ? clk->table[i] : clk->table[i + 1];  in r9a06g032_div_clamp_div()
611 	u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);  in r9a06g032_div_determine_rate()
614 		 hw->clk, req->rate, req->best_parent_rate, div);  in r9a06g032_div_determine_rate()
616 		 clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),  in r9a06g032_div_determine_rate()
617 		 clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));  in r9a06g032_div_determine_rate()
619 	div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);  in r9a06g032_div_determine_rate()
622 	 * that is 16 times the baud rate -- and that is wildly outside the  in r9a06g032_div_determine_rate()
629 	if (clk->index == R9A06G032_DIV_UART ||  in r9a06g032_div_determine_rate()
630 	    clk->index == R9A06G032_DIV_P2_PG) {  in r9a06g032_div_determine_rate()
632 		req->rate = clk_get_rate(hw->clk);  in r9a06g032_div_determine_rate()
635 	req->rate = DIV_ROUND_UP(req->best_parent_rate, div);  in r9a06g032_div_determine_rate()
636 	pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,  in r9a06g032_div_determine_rate()
637 		 req->best_parent_rate, div, req->rate);  in r9a06g032_div_determine_rate()
648 	u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);  in r9a06g032_div_set_rate()
650 	pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,  in r9a06g032_div_set_rate()
685 	init.name = desc->name;  in r9a06g032_register_div()
691 	div->clocks = clocks;  in r9a06g032_register_div()
692 	div->index = desc->index;  in r9a06g032_register_div()
693 	div->reg = desc->reg;  in r9a06g032_register_div()
694 	div->hw.init = &init;  in r9a06g032_register_div()
695 	div->min = desc->div_min;  in r9a06g032_register_div()
696 	div->max = desc->div_max;  in r9a06g032_register_div()
698 	for (i = 0; i < ARRAY_SIZE(div->table) &&  in r9a06g032_register_div()
699 	     i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {  in r9a06g032_register_div()
700 		div->table[div->table_size++] = desc->div_table[i];  in r9a06g032_register_div()
703 	clk = clk_register(NULL, &div->hw);  in r9a06g032_register_div()
712  * This clock provider handles the case of the R9A06G032 where you have
714  * each of the clock source - the used clock source (for all sub clocks)
716  * That single bit affects all sub-clocks, and therefore needs to change the
737 	return clk_rdesc_get(set->clocks, set->selector);  in r9a06g032_clk_mux_get_parent()
745 	clk_rdesc_set(set->clocks, set->selector, !!index);  in r9a06g032_clk_mux_set_parent()
773 	init.name = desc->name;  in r9a06g032_register_bitsel()
779 	g->clocks = clocks;  in r9a06g032_register_bitsel()
780 	g->index = desc->index;  in r9a06g032_register_bitsel()
781 	g->selector = desc->dual.sel;  in r9a06g032_register_bitsel()
782 	g->hw.init = &init;  in r9a06g032_register_bitsel()
784 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_bitsel()
806 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_setenable()
809 	r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);  in r9a06g032_clk_dualgate_setenable()
810 	r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);  in r9a06g032_clk_dualgate_setenable()
834 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_is_enabled()
836 	return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);  in r9a06g032_clk_dualgate_is_enabled()
859 	g->clocks = clocks;  in r9a06g032_register_dualgate()
860 	g->index = desc->index;  in r9a06g032_register_dualgate()
861 	g->selector = sel;  in r9a06g032_register_dualgate()
862 	g->gate[0].gate = desc->dual.g1;  in r9a06g032_register_dualgate()
863 	g->gate[0].reset = desc->dual.r1;  in r9a06g032_register_dualgate()
864 	g->gate[1].gate = desc->dual.g2;  in r9a06g032_register_dualgate()
865 	g->gate[1].reset = desc->dual.r2;  in r9a06g032_register_dualgate()
867 	init.name = desc->name;  in r9a06g032_register_dualgate()
872 	g->hw.init = &init;  in r9a06g032_register_dualgate()
878 	if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {  in r9a06g032_register_dualgate()
880 		pr_debug("%s was enabled, making read-only\n", desc->name);  in r9a06g032_register_dualgate()
883 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_dualgate()
898 	struct device *dev = &pdev->dev;  in r9a06g032_clocks_probe()
899 	struct device_node *np = dev->of_node;  in r9a06g032_clocks_probe()
911 		return -ENOMEM;  in r9a06g032_clocks_probe()
913 	spin_lock_init(&clocks->lock);  in r9a06g032_clocks_probe()
915 	clocks->data.clks = clks;  in r9a06g032_clocks_probe()
916 	clocks->data.clk_num = R9A06G032_CLOCK_COUNT;  in r9a06g032_clocks_probe()
922 	clocks->reg = of_iomap(np, 0);  in r9a06g032_clocks_probe()
923 	if (WARN_ON(!clocks->reg))  in r9a06g032_clocks_probe()
924 		return -ENOMEM;  in r9a06g032_clocks_probe()
927 		const char *parent_name = d->source ?  in r9a06g032_clocks_probe()
928 			__clk_get_name(clocks->data.clks[d->source - 1]) :  in r9a06g032_clocks_probe()
932 		switch (d->type) {  in r9a06g032_clocks_probe()
934 			clk = clk_register_fixed_factor(NULL, d->name,  in r9a06g032_clocks_probe()
936 							d->mul, d->div);  in r9a06g032_clocks_probe()
946 			uart_group_sel[d->dual.group] = d->dual.sel;  in r9a06g032_clocks_probe()
952 							  uart_group_sel[d->dual.group]);  in r9a06g032_clocks_probe()
955 		clocks->data.clks[d->index] = clk;  in r9a06g032_clocks_probe()
957 	error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);  in r9a06g032_clocks_probe()
970 	{ .compatible = "renesas,r9a06g032-sysctrl" },
976 		.name	= "renesas,r9a06g032-sysctrl",