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/Linux-v5.10/drivers/pinctrl/zte/
Dpinctrl-zx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * struct zx_mux_desc - hardware mux descriptor
21 * struct zx_pin_data - hardware per-pin data
23 * @offset: register offset within TOP pinmux controller
24 * @bitpos: bit position within TOP pinmux register
25 * @width: bit width within TOP pinmux register
30 * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
31 * arbitrarily, AON pinmux register bits are well organized per pin id, and
33 * and bit position from pin id. Thus, we only need to define TOP pinmux and
/Linux-v5.10/arch/arm64/boot/dts/mediatek/
Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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Dmt2712-evb.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
26 stdout-path = "serial0:921600n8";
30 compatible = "regulator-fixed";
31 regulator-name = "vproc_buck0";
32 regulator-min-microvolt = <1000000>;
33 regulator-max-microvolt = <1000000>;
37 compatible = "regulator-fixed";
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Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 clock-output-names = "clk32k";
35 compatible = "regulator-fixed";
36 regulator-name = "it6505_pp18";
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Dmt8173-evb.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
30 compatible = "hdmi-connector";
36 remote-endpoint = <&hdmi0_out>;
42 compatible = "linux,extcon-usb-gpio";
43 id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
47 compatible = "regulator-fixed";
48 regulator-name = "usb_vbus";
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/Linux-v5.10/Documentation/devicetree/bindings/pinctrl/
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Pinmux & GPIO controller controls pin multiplexing & configuration including
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
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Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
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Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
50 For cases like this, the pin controller driver may use pinctrl-pin-array helper
55 #pinctrl-cells = <2>;
58 pinctrl-pin-array = <
67 Above #pinctrl-cells specifies the number of value cells in addition to the
68 index of the registers. This is similar to the interrupts-extended binding with
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Drenesas,rza2-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
23 const: "renesas,r7s9210-pinctrl" # RZ/A2M
28 gpio-controller: true
30 '#gpio-cells':
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Dpinctrl-mt8192.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
38 reg-names:
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Drenesas,rza1-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
25 - const: renesas,r7s72100-ports # RZ/A1H
26 - items:
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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Dfsl,mxs-pinctrl.txt6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
20 information about pull-up. For this reason, even seemingly boolean values are
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
41 Required subnode-properties:
42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
56 - reg: Should be the index of the group nodes for same function. This property
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Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
15 - compatible: "syscon"
19 const: mediatek,mt6779-pinctrl
25 reg-names:
27 - const: "gpio"
28 - const: "iocfg_rm"
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Dactions,s500-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi S500 SoC pinmux & GPIO controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
14 Pinmux & GPIO controller manages pin multiplexing & configuration including
16 pinctrl-bindings.txt in this directory for common binding part and usage.
20 const: actions,s500-pinctrl
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/Linux-v5.10/arch/arm/boot/dts/
Dat91-kizbox3-hs.dts1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
11 /dts-v1/;
12 #include "at91-kizbox3_common.dtsi"
15 model = "Overkiz KIZBOX3-HS";
16 compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_led_red
48 default-state = "off";
[all …]
Dmt2701-evb.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
22 compatible = "mediatek,mt2701-cs42448-machine";
25 audio-routing =
42 mediatek,audio-codec = <&cs42448>;
43 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&aud_pins_default>;
[all …]
/Linux-v5.10/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
17 #include "pinmux.h"
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
[all …]
/Linux-v5.10/drivers/pinctrl/mediatek/
Dpinctrl-moore.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018 MediaTek Inc.
17 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf-generic.h>
23 #include "../pinmux.h"
24 #include "mtk-eint.h"
25 #include "pinctrl-mtk-common-v2.h"
40 #define PINCTRL_PIN_GROUP(name, id) \ argument
43 id##_pins, \
44 ARRAY_SIZE(id##_pins), \
[all …]
Dpinctrl-paris.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf-generic.h>
24 #include "../pinctrl-utils.h"
25 #include "../pinmux.h"
26 #include "mtk-eint.h"
27 #include "pinctrl-mtk-common-v2.h"
52 #define PINCTRL_PIN_GROUP(name, id) \ argument
55 id##_pins, \
56 ARRAY_SIZE(id##_pins), \
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/Linux-v5.10/drivers/pinctrl/renesas/
Dpinctrl-rza1.c1 // SPDX-License-Identifier: GPL-2.0
11 * This includes SoCs which are sub- or super- sets of this particular line,
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinmux.h>
32 #include "../pinmux.h"
34 #define DRIVER_NAME "pinctrl-rza1"
52 #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) argument
53 #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) argument
74 /* ----------------------------------------------------------------------------
75 * RZ/A1 pinmux flags
[all …]
/Linux-v5.10/drivers/mfd/
Dsi476x-i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/si476x-i2c.c -- Core device driver for si476x MFD
21 #include <linux/mfd/si476x-core.h>
27 * si476x_core_config_pinmux() - pin function configuration function
39 dev_dbg(&core->client->dev, "Configuring pinmux\n"); in si476x_core_config_pinmux()
41 core->pinmux.dclk, in si476x_core_config_pinmux()
42 core->pinmux.dfs, in si476x_core_config_pinmux()
43 core->pinmux.dout, in si476x_core_config_pinmux()
44 core->pinmux.xout); in si476x_core_config_pinmux()
46 dev_err(&core->client->dev, in si476x_core_config_pinmux()
[all …]
/Linux-v5.10/drivers/pinctrl/freescale/
Dpinctrl-imx1.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * IMX pinmux core definitions
17 * struct imx1_pin - describes an IMX1/21/27 pin.
18 * @pin_id: ID of the described pin.
19 * @mux_id: ID of the mux setup.
20 * @config: Configuration of the pin (currently only pullup-enable).
29 * struct imx1_pin_group - describes an IMX pin group
43 * struct imx1_pmx_func - describes IMX pinmux functions
/Linux-v5.10/drivers/pinctrl/tegra/
Dpinctrl-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Pinctrl data for the NVIDIA Tegra194 pinmux
21 #include <linux/pinctrl/pinmux.h>
23 #include "pinctrl-tegra.h"
25 /* Define unique ID for each pins */
45 /* Define unique ID for each function */
85 .lpmd_bit = -1, \
86 .lock_bit = -1, \
87 .hsm_bit = -1, \
104 DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
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/Linux-v5.10/arch/arm64/boot/dts/qcom/
Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &hyp_mem;
24 /delete-node/ &xbl_mem;
25 /delete-node/ &aop_mem;
26 /delete-node/ &sec_apps_mem;
27 /delete-node/ &tz_mem;
35 reserved-memory {
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