| /Linux-v5.4/drivers/nfc/s3fwrn5/ |
| D | i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
34 enum s3fwrn5_mode mode; member
40 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_wake() local
42 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_wake()
43 gpio_set_value(phy->gpio_fw_wake, wake); in s3fwrn5_i2c_set_wake()
45 mutex_unlock(&phy->mutex); in s3fwrn5_i2c_set_wake()
48 static void s3fwrn5_i2c_set_mode(void *phy_id, enum s3fwrn5_mode mode) in s3fwrn5_i2c_set_mode() argument
50 struct s3fwrn5_i2c_phy *phy = phy_id; in s3fwrn5_i2c_set_mode() local
52 mutex_lock(&phy->mutex); in s3fwrn5_i2c_set_mode()
54 if (phy->mode == mode) in s3fwrn5_i2c_set_mode()
[all …]
|
| /Linux-v5.4/drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
87 struct mipi_phy_params phy; member
120 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
150 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
151 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
153 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
154 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
155 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
189 phy->pll_fbd_p = 0; in dsi_calc_phy_rate()
[all …]
|
| /Linux-v5.4/include/linux/phy/ |
| D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * phy.h -- generic phy header file
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
19 #include <linux/phy/phy-mipi-dphy.h>
21 struct phy;
45 * union phy_configure_opts - Opaque generic phy configuration
48 * the MIPI_DPHY phy mode.
55 * struct phy_ops - set of function pointers for performing phy operations
56 * @init: operation to be performed for initializing phy
58 * @power_on: powering on the phy
[all …]
|
| /Linux-v5.4/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
13 #include <linux/arm-smccc.h>
18 #include <linux/phy.h>
19 #include <linux/phy/phy.h>
29 #define COMPHY_FW_NOT_SUPPORTED (-1)
51 #define COMPHY_FW_MODE(mode) ((mode) << 12) argument
52 #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ argument
55 #define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ argument
60 enum phy_mode mode; member
[all …]
|
| /Linux-v5.4/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
75 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
80 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode() local
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/phy/ |
| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
17 but a fixed mode setting, the property should be present to specify
[all …]
|
| D | ti-phy-gmii-sel.txt | 1 CPSW Port's Interface Mode Selection PHY Tree Bindings
2 -----------------------------------------------
6 The interface mode is selected by configuring the MII mode selection register(s)
10 +--------------+
11 +-------------------------------+ |SCM |
12 | CPSW | | +---------+ |
13 | +--------------------------------+gmii_sel | |
14 | | | | +---------+ |
15 | +----v---+ +--------+ | +--------------+
16 | |Port 1..<--+-->GMII/MII<------->
[all …]
|
| D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
[all …]
|
| /Linux-v5.4/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
181 enum pipe3_mode mode; member
206 enum pipe3_mode mode; member
212 .mode = PIPE3_MODE_USBSS,
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
238 .mode = PIPE3_MODE_SATA,
[all …]
|
| /Linux-v5.4/drivers/phy/amlogic/ |
| D | phy-meson-gxl-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Meson GXL and GXM USB2 PHY driver
15 #include <linux/phy/phy.h>
18 /* bits [31:27] are read-only */
66 /* bits [31:14] are read-only */
94 enum phy_mode mode; member
107 static int phy_meson_gxl_usb2_init(struct phy *phy) in phy_meson_gxl_usb2_init() argument
109 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb2_init()
112 ret = reset_control_reset(priv->reset); in phy_meson_gxl_usb2_init()
116 ret = clk_prepare_enable(priv->clk); in phy_meson_gxl_usb2_init()
[all …]
|
| D | phy-meson-gxl-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Meson GXL USB3 PHY and OTG mode detection driver
13 #include <linux/phy/phy.h>
78 /* read-only register */
85 enum phy_mode mode; member
98 static int phy_meson_gxl_usb3_power_on(struct phy *phy) in phy_meson_gxl_usb3_power_on() argument
100 struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy); in phy_meson_gxl_usb3_power_on()
102 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, in phy_meson_gxl_usb3_power_on()
104 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, in phy_meson_gxl_usb3_power_on()
106 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK, in phy_meson_gxl_usb3_power_on()
[all …]
|
| D | phy-meson-g12a-usb3-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
58 struct phy *phy; member
59 unsigned int mode; member
77 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
78 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
82 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 6 - compatible: may be compatible = "mediatek,mt7530"
8 - #address-cells: Must be 1.
9 - #size-cells: Must be 0.
10 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
11 on multi-chip module belong to MT7623A has or the remotely standalone
16 - core-supply: Phandle to the regulator node necessary for the core power.
17 - io-supply: Phandle to the regulator node necessary for the I/O power.
18 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
23 - reset-gpios: Should be a gpio specifier for a reset line.
27 - resets : Phandle pointing to the system reset controller with
[all …]
|
| D | sja1105.txt | 6 - compatible:
8 - "nxp,sja1105e"
9 - "nxp,sja1105t"
10 - "nxp,sja1105p"
11 - "nxp,sja1105q"
12 - "nxp,sja1105r"
13 - "nxp,sja1105s"
18 and the non-SGMII devices, while pin-compatible, are not equal in terms
24 - sja1105,role-mac:
25 - sja1105,role-phy:
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/usb/ |
| D | dwc2.txt | 2 -----------------------------------------------------
5 - compatible : One of:
6 - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
7 - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
8 - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
9 - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
10 - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
11 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
12 - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
13 - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
[all …]
|
| /Linux-v5.4/drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); in csiphy_routing_cfg_3630()
41 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
49 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
53 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
57 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
59 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
[all …]
|
| /Linux-v5.4/drivers/net/ |
| D | sungem_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY drivers for the sungem ethernet driver.
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
39 /* Link modes of the BCM5400 PHY */
51 static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) in __sungem_phy_read() argument
53 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
[all …]
|
| /Linux-v5.4/drivers/phy/st/ |
| D | phy-spear1340-miphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
32 /* PCIE - SATA configuration registers */
80 /* phy mode: 0 for SATA 1 for PCIe */
81 enum spear1340_miphy_mode mode; member
84 /* phy struct pointer */
85 struct phy *phy; member
90 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
[all …]
|
| D | socionext,uniphier-ave4.txt | 7 - compatible: Should be
8 - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
9 - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
10 - "socionext,uniphier-ld11-ave4" : for LD11 SoC
11 - "socionext,uniphier-ld20-ave4" : for LD20 SoC
12 - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC
13 - reg: Address where registers are mapped and size of region.
14 - interrupts: Should contain the MAC interrupt.
15 - phy-mode: See ethernet.txt in the same directory. Allow to choose
16 "rgmii", "rmii", "mii", or "internal" according to the PHY.
[all …]
|
| D | micrel.txt | 1 Micrel PHY properties.
7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
20 See the respective PHY datasheet for the mode values.
22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
26 than 50 MHz clock mode.
28 Note that this option in only needed for certain PHY revisions with a
29 non-standard, inverted function of this configuration bit.
30 Specifically, a clock reference ("rmii-ref" below) is always needed to
[all …]
|
| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]
|
| D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
[all …]
|
| /Linux-v5.4/arch/arm/boot/dts/ |
| D | ls1021a-tsn.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
12 sys_mclk: clock-mclk {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <24576000>;
18 reg_vdda_codec: regulator-3V3 {
19 compatible = "regulator-fixed";
[all …]
|
| /Linux-v5.4/drivers/phy/lantiq/ |
| D | phy-lantiq-vrx200-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
8 * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
11 * TODO: PHY modes other than 36MHz (without "SSC")
21 #include <linux/phy/phy.h>
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
85 struct phy *phy; member
86 unsigned int mode; member
98 static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy) in ltq_vrx200_pcie_phy_common_setup() argument
100 struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy); in ltq_vrx200_pcie_phy_common_setup()
[all …]
|
