Lines Matching +full:phy +full:- +full:mode

1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10   - Alexandru Ardelean <alexandru.ardelean@analog.com>
16   - $ref: ethernet-phy.yaml#
19   adi,rx-internal-delay-ps:
21       RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22       internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26   adi,tx-internal-delay-ps:
28       RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29       internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33   adi,fifo-depth-bits:
35       When operating in RMII mode, this option configures the FIFO depth.
40   - |
42         #address-cells = <1>;
43         #size-cells = <0>;
45         phy-mode = "rgmii-id";
47         ethernet-phy@0 {
50             adi,rx-internal-delay-ps = <1800>;
51             adi,tx-internal-delay-ps = <2200>;
54   - |
56         #address-cells = <1>;
57         #size-cells = <0>;
59         phy-mode = "rmii";
61         ethernet-phy@1 {
64             adi,fifo-depth-bits = <16>;