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Searched +full:enet +full:- +full:phy +full:- +full:lane +full:- +full:swap (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.15/arch/arm64/boot/dts/broadcom/stingray/
Dbcm958742t.dts33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
Dbcm958742k.dts4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
59 pinctrl-0 = <&spi0_pins>;
60 pinctrl-names = "default";
61 cs-gpios = <&gpio_hsls 34 0>;
64 spi-flash@0 {
65 compatible = "jedec,spi-nor";
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/Linux-v5.15/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
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/Linux-v5.15/arch/arm64/boot/dts/broadcom/northstar2/
Dns2-svk.dts33 /dts-v1/;
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
59 &enet {
113 spi-max-frequency = <5000000>;
114 spi-cpha = <1>;
115 spi-cpol = <1>;
118 pl022,slave-tx-disable = <0>;
119 pl022,com-mode = <0>;
120 pl022,rx-level-trig = <1>;
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/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mp-phyboard-pollux-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/leds/leds-pca9532.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-som.dtsi"
14 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
15 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
16 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
19 stdout-path = &uart1;
22 reg_usdhc2_vmmc: regulator-usdhc2 {
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Dimx8mp-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
26 cpu-supply = <&buck2>;
30 cpu-supply = <&buck2>;
34 cpu-supply = <&buck2>;
38 cpu-supply = <&buck2>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_fec>;
[all …]
/Linux-v5.15/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
18 #include <dt-bindings/net/ti-dp83867.h>
98 /* PHY CTRL bits */
123 /* PHY STS bits */
183 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
195 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
196 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
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Ddp83869.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83869 PHY
12 #include <linux/phy.h>
16 #include <dt-bindings/net/ti-dp83869.h>
69 /* This is the same bit mask as the BMCR so re-use the BMCR default */
157 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status()
164 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { in dp83869_read_status()
165 if (phydev->link) { in dp83869_read_status()
166 if (dp83869->mode == DP83869_RGMII_100_BASE) in dp83869_read_status()
167 phydev->speed = SPEED_100; in dp83869_read_status()
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Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/broadcom.c
13 #include "bcm-phy-lib.h"
15 #include <linux/phy.h>
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25 MODULE_DESCRIPTION("Broadcom PHY driver");
33 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
36 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
37 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
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/Linux-v5.15/arch/arm/boot/dts/
Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
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