Lines Matching +full:enet +full:- +full:phy +full:- +full:lane +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83867 PHY
12 #include <linux/phy.h>
18 #include <dt-bindings/net/ti-dp83867.h>
98 /* PHY CTRL bits */
123 /* PHY STS bits */
183 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
195 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
196 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
199 return -EINVAL; in dp83867_set_wol()
213 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
215 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
217 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
219 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
226 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
231 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
251 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
253 wol->wolopts = 0; in dp83867_get_wol()
258 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
261 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
264 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
269 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
270 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
274 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
275 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
279 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
280 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
282 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
286 wol->wolopts = 0; in dp83867_get_wol()
293 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
360 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
362 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
365 phydev->speed = SPEED_1000; in dp83867_read_status()
367 phydev->speed = SPEED_100; in dp83867_read_status()
369 phydev->speed = SPEED_10; in dp83867_read_status()
399 return -EINVAL; in dp83867_get_downshift()
412 return -E2BIG; in dp83867_set_downshift()
434 return -EINVAL; in dp83867_set_downshift()
448 switch (tuna->id) { in dp83867_get_tunable()
452 return -EOPNOTSUPP; in dp83867_get_tunable()
459 switch (tuna->id) { in dp83867_set_tunable()
463 return -EOPNOTSUPP; in dp83867_set_tunable()
470 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
472 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
483 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
488 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
499 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
500 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
505 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
506 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
507 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
508 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
509 return -EINVAL; in dp83867_verify_rgmii_cfg()
513 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
514 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
515 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
516 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
517 return -EINVAL; in dp83867_verify_rgmii_cfg()
526 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
527 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
528 struct device_node *of_node = dev->of_node; in dp83867_of_init()
532 return -ENODEV; in dp83867_of_init()
535 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
536 &dp83867->clk_output_sel); in dp83867_of_init()
539 dp83867->set_clk_output = true; in dp83867_of_init()
543 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
544 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
545 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
546 dp83867->clk_output_sel); in dp83867_of_init()
547 return -EINVAL; in dp83867_of_init()
551 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init()
552 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init()
553 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init()
554 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init()
556 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init()
558 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
559 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
561 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
562 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
564 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
565 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
566 &dp83867->rx_id_delay); in dp83867_of_init()
567 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
569 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
570 dp83867->rx_id_delay); in dp83867_of_init()
571 return -EINVAL; in dp83867_of_init()
574 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
575 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
576 &dp83867->tx_id_delay); in dp83867_of_init()
577 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
579 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
580 dp83867->tx_id_delay); in dp83867_of_init()
581 return -EINVAL; in dp83867_of_init()
584 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
585 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
587 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
588 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
590 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
591 &dp83867->tx_fifo_depth); in dp83867_of_init()
593 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
594 &dp83867->tx_fifo_depth); in dp83867_of_init()
596 dp83867->tx_fifo_depth = in dp83867_of_init()
600 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
601 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
602 dp83867->tx_fifo_depth); in dp83867_of_init()
603 return -EINVAL; in dp83867_of_init()
606 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
607 &dp83867->rx_fifo_depth); in dp83867_of_init()
609 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
611 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
612 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
613 dp83867->rx_fifo_depth); in dp83867_of_init()
614 return -EINVAL; in dp83867_of_init()
630 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
633 return -ENOMEM; in dp83867_probe()
635 phydev->priv = dp83867; in dp83867_probe()
642 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
646 /* Force speed optimization for the PHY even if it strapped */ in dp83867_config_init()
657 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
664 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
676 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
682 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
685 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
687 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
704 * Such N/A mode enabled by mistake can put PHY IC in some in dp83867_config_init()
720 * aligned mode as one might expect. Instead we use the PHY's default in dp83867_config_init()
729 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
732 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
735 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
741 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
742 delay |= dp83867->rx_id_delay; in dp83867_config_init()
743 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
744 delay |= dp83867->tx_id_delay << in dp83867_config_init()
752 if (dp83867->io_impedance >= 0) in dp83867_config_init()
755 dp83867->io_impedance); in dp83867_config_init()
757 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
784 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
786 * switch on 6-wire mode. in dp83867_config_init()
788 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
803 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
807 if (dp83867->set_clk_output) { in dp83867_config_init()
810 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
814 val = dp83867->clk_output_sel << in dp83867_config_init()
874 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");