Home
last modified time | relevance | path

Searched full:pmu (Results 1 – 25 of 808) sorted by relevance

12345678910>>...33

/Linux-v5.4/arch/x86/kvm/vmx/
Dpmu_intel.c3 * KVM PMU support for Intel CPUs
18 #include "pmu.h"
35 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) in reprogram_fixed_counters() argument
39 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { in reprogram_fixed_counters()
41 u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i); in reprogram_fixed_counters()
44 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); in reprogram_fixed_counters()
52 pmu->fixed_ctr_ctrl = data; in reprogram_fixed_counters()
56 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data) in global_ctrl_changed() argument
59 u64 diff = pmu->global_ctrl ^ data; in global_ctrl_changed()
61 pmu->global_ctrl = data; in global_ctrl_changed()
[all …]
/Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c32 struct nvkm_pmu *pmu = device->pmu; in nvkm_pmu_fan_controlled() local
34 /* Internal PMU FW does not currently control fans in any way, in nvkm_pmu_fan_controlled()
37 if (pmu && pmu->func->code.size) in nvkm_pmu_fan_controlled()
40 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi in nvkm_pmu_fan_controlled()
48 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) in nvkm_pmu_pgob() argument
50 if (pmu && pmu->func->pgob) in nvkm_pmu_pgob()
51 pmu->func->pgob(pmu, enable); in nvkm_pmu_pgob()
57 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); in nvkm_pmu_recv() local
58 return pmu->func->recv(pmu); in nvkm_pmu_recv()
62 nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in nvkm_pmu_send() argument
[all …]
Dgk20a.c51 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_target() argument
53 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_target()
59 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_get_cur_state() argument
61 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_cur_state()
67 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_target_state() argument
70 struct gk20a_pmu_dvfs_data *data = pmu->data; in gk20a_pmu_dvfs_get_target_state()
71 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_target_state()
86 nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n", in gk20a_pmu_dvfs_get_target_state()
95 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_dev_status() argument
98 struct nvkm_falcon *falcon = pmu->base.falcon; in gk20a_pmu_dvfs_get_dev_status()
[all …]
Dgt215.c30 gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in gt215_pmu_send() argument
33 struct nvkm_subdev *subdev = &pmu->subdev; in gt215_pmu_send()
50 * on a synchronous reply, take the PMU mutex and tell the in gt215_pmu_send()
54 pmu->recv.message = message; in gt215_pmu_send()
55 pmu->recv.process = process; in gt215_pmu_send()
65 pmu->send.base)); in gt215_pmu_send()
77 wait_event(pmu->recv.wait, (pmu->recv.process == 0)); in gt215_pmu_send()
78 reply[0] = pmu->recv.data[0]; in gt215_pmu_send()
79 reply[1] = pmu->recv.data[1]; in gt215_pmu_send()
87 gt215_pmu_recv(struct nvkm_pmu *pmu) in gt215_pmu_recv() argument
[all …]
DKbuild2 nvkm-y += nvkm/subdev/pmu/base.o
3 nvkm-y += nvkm/subdev/pmu/memx.o
4 nvkm-y += nvkm/subdev/pmu/gt215.o
5 nvkm-y += nvkm/subdev/pmu/gf100.o
6 nvkm-y += nvkm/subdev/pmu/gf119.o
7 nvkm-y += nvkm/subdev/pmu/gk104.o
8 nvkm-y += nvkm/subdev/pmu/gk110.o
9 nvkm-y += nvkm/subdev/pmu/gk208.o
10 nvkm-y += nvkm/subdev/pmu/gk20a.o
11 nvkm-y += nvkm/subdev/pmu/gm107.o
[all …]
/Linux-v5.4/drivers/soc/dove/
Dpmu.c3 * Marvell Dove PMU support
17 #include <linux/soc/dove/pmu.h>
42 * The PMU contains a register to reset various subsystems within the
50 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_reset() local
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
58 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_reset()
65 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_assert() local
[all …]
/Linux-v5.4/drivers/perf/
Dfsl_imx8_ddr_perf.c40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
61 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
62 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 struct pmu pmu; member
84 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
86 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
181 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event) in ddr_perf_alloc_counter() argument
191 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL) in ddr_perf_alloc_counter()
198 if (pmu->events[i] == NULL) in ddr_perf_alloc_counter()
205 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_free_counter() argument
[all …]
Darm_pmu_platform.c25 static int probe_current_pmu(struct arm_pmu *pmu, in probe_current_pmu() argument
32 pr_info("probing PMU on CPU %d\n", cpu); in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
45 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq) in pmu_parse_percpu_irq() argument
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
96 static int pmu_parse_irqs(struct arm_pmu *pmu) in pmu_parse_irqs() argument
99 struct platform_device *pdev = pmu->plat_device; in pmu_parse_irqs()
100 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_irqs()
[all …]
Darm_pmu.c105 if (type == event->pmu->type) in armpmu_map_event()
122 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_set_period()
164 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_update()
194 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_stop()
198 * ARM pmu always has to update the counter, so ignore in armpmu_stop()
210 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_start()
214 * ARM pmu always has to reprogram the period, so ignore in armpmu_start()
235 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_del()
251 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_add()
284 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, in validate_event() argument
[all …]
Darm_pmu_acpi.c33 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't in arm_pmu_acpi_register_irq()
90 * For lack of a better place, hook the normal PMU MADT walk
152 pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n", in arm_pmu_acpi_parse_irqs()
156 pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu); in arm_pmu_acpi_parse_irqs()
194 struct arm_pmu *pmu; in arm_pmu_acpi_find_alloc_pmu() local
198 pmu = per_cpu(probed_pmus, cpu); in arm_pmu_acpi_find_alloc_pmu()
199 if (!pmu || pmu->acpi_cpuid != cpuid) in arm_pmu_acpi_find_alloc_pmu()
202 return pmu; in arm_pmu_acpi_find_alloc_pmu()
205 pmu = armpmu_alloc_atomic(); in arm_pmu_acpi_find_alloc_pmu()
206 if (!pmu) { in arm_pmu_acpi_find_alloc_pmu()
[all …]
Darm_dsu_pmu.c3 * ARM DynamIQ Shared Unit (DSU) PMU driver
7 * Based on ARM CCI-PMU, ARMv8 PMU-v3 drivers.
33 /* PMU event codes */
59 * bit maps in the PMU registers (e.g CLUSTERPMSELR).
98 * struct dsu_pmu - DSU PMU descriptor
100 * @pmu_lock : Protects accesses to DSU PMU register from normal vs
104 * @active_cpu : CPU to which the PMU is bound for accesses.
106 * @num_counters : Number of event counters implemented by the PMU,
113 struct pmu pmu; member
127 static inline struct dsu_pmu *to_dsu_pmu(struct pmu *pmu) in to_dsu_pmu() argument
[all …]
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_pmu.c80 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) in pmu_needs_timer() argument
82 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); in pmu_needs_timer()
90 enable = pmu->enable; in pmu_needs_timer()
121 struct i915_pmu *pmu = &i915->pmu; in i915_pmu_gt_parked() local
123 if (!pmu->base.event_init) in i915_pmu_gt_parked()
126 spin_lock_irq(&pmu->lock); in i915_pmu_gt_parked()
131 pmu->timer_enabled = pmu_needs_timer(pmu, false); in i915_pmu_gt_parked()
132 spin_unlock_irq(&pmu->lock); in i915_pmu_gt_parked()
135 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu) in __i915_pmu_maybe_start_timer() argument
137 if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) { in __i915_pmu_maybe_start_timer()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/arm/
Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
24 - arm,cortex-a73-pmu
25 - arm,cortex-a72-pmu
26 - arm,cortex-a57-pmu
27 - arm,cortex-a53-pmu
28 - arm,cortex-a35-pmu
29 - arm,cortex-a17-pmu
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
[all …]
/Linux-v5.4/arch/x86/kvm/
Dpmu_amd.c3 * KVM PMU support for AMD
18 #include "pmu.h"
47 static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type) in get_msr_base() argument
49 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); in get_msr_base()
98 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr, in get_gp_pmc_amd() argument
126 return &pmu->gp_counters[msr_to_index(msr)]; in get_gp_pmc_amd()
129 static unsigned amd_find_arch_event(struct kvm_pmu *pmu, in amd_find_arch_event() argument
160 static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) in amd_pmc_idx_to_pmc() argument
162 unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER); in amd_pmc_idx_to_pmc()
163 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); in amd_pmc_idx_to_pmc()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/perf/
Dapm-xgene-pmu.txt1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
4 The following PMU devices are supported:
11 The following section describes the SoC PMU DT node binding.
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
19 - reg : First resource shall be the CPU bus PMU resource.
20 - interrupts : Interrupt-specifier for PMU IRQ.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
[all …]
/Linux-v5.4/virt/kvm/arm/
Dpmu.c34 struct kvm_pmu *pmu; in kvm_pmc_to_vcpu() local
38 pmu = container_of(pmc, struct kvm_pmu, pmc[0]); in kvm_pmc_to_vcpu()
39 vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu); in kvm_pmc_to_vcpu()
45 * @pmc: The PMU counter pointer
51 return test_bit(pmc->idx >> 1, vcpu->arch.pmu.chained); in kvm_pmu_pmc_is_chained()
65 * @pmc: The PMU counter pointer
100 * kvm_pmu_get_pair_counter_value - get PMU counter value
102 * @pmc: The PMU counter pointer
135 * kvm_pmu_get_counter_value - get PMU counter value
142 struct kvm_pmu *pmu = &vcpu->arch.pmu; in kvm_pmu_get_counter_value() local
[all …]
/Linux-v5.4/arch/x86/events/intel/
Drapl.c53 #define pr_fmt(fmt) "RAPL PMU: " fmt
119 struct pmu *pmu; member
125 struct pmu pmu; member
211 static void rapl_start_hrtimer(struct rapl_pmu *pmu) in rapl_start_hrtimer() argument
213 hrtimer_start(&pmu->hrtimer, pmu->timer_interval, in rapl_start_hrtimer()
219 struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer); in rapl_hrtimer_handle() local
223 if (!pmu->n_active) in rapl_hrtimer_handle()
226 raw_spin_lock_irqsave(&pmu->lock, flags); in rapl_hrtimer_handle()
228 list_for_each_entry(event, &pmu->active_list, active_entry) in rapl_hrtimer_handle()
231 raw_spin_unlock_irqrestore(&pmu->lock, flags); in rapl_hrtimer_handle()
[all …]
Duncore.c103 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu) in uncore_pmu_to_box() argument
111 return dieid < max_dies ? pmu->boxes[dieid] : NULL; in uncore_pmu_to_box()
342 * Using uncore_pmu_event_init pmu event_init callback
349 return &box->pmu->pmu == event->pmu; in is_box_event()
359 max_count = box->pmu->type->num_counters; in uncore_collect_events()
360 if (box->pmu->type->fixed_ctl) in uncore_collect_events()
393 struct intel_uncore_type *type = box->pmu->type; in uncore_get_event_constraint()
418 if (box->pmu->type->ops->put_constraint) in uncore_put_event_constraint()
419 box->pmu->type->ops->put_constraint(box, event); in uncore_put_event_constraint()
655 * PMU if it was the only group available.
[all …]
Duncore.h75 struct pmu *pmu; /* for custom pmu ops */ member
97 struct pmu pmu; member
127 struct intel_uncore_pmu *pmu; member
201 return box->pmu->type->box_ctl + in uncore_mmio_box_ctl()
202 box->pmu->type->mmio_offset * box->pmu->pmu_idx; in uncore_mmio_box_ctl()
207 return box->pmu->type->box_ctl; in uncore_pci_box_ctl()
212 return box->pmu->type->fixed_ctl; in uncore_pci_fixed_ctl()
217 return box->pmu->type->fixed_ctr; in uncore_pci_fixed_ctr()
224 return idx * 8 + box->pmu->type->event_ctl; in uncore_pci_event_ctl()
226 return idx * 4 + box->pmu->type->event_ctl; in uncore_pci_event_ctl()
[all …]
/Linux-v5.4/arch/powerpc/perf/
Dimc-pmu.c12 #include <asm/imc-pmu.h>
20 * Used to avoid races in counting the nest-pmu units during hotplug
49 return container_of(event->pmu, struct imc_pmu, pmu); in imc_event_to_pmu()
93 struct pmu *pmu = dev_get_drvdata(dev); in imc_pmu_cpumask_get_attr() local
94 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu); in imc_pmu_cpumask_get_attr()
207 * and assign the attr_group to the pmu "pmu".
209 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu) in update_events_in_group() argument
246 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL); in update_events_in_group()
247 if (!pmu->events) in update_events_in_group()
253 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]); in update_events_in_group()
[all …]
DMakefile6 obj64-$(CONFIG_PPC_PERF_CTRS) += ppc970-pmu.o power5-pmu.o \
7 power5+-pmu.o power6-pmu.o power7-pmu.o \
8 isa207-common.o power8-pmu.o power9-pmu.o \
9 generic-compat-pmu.o
10 obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
12 obj-$(CONFIG_PPC_POWERNV) += imc-pmu.o
14 obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
18 obj-$(CONFIG_PPC_8xx) += 8xx-pmu.o
/Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dgm200.c28 #include <subdev/bios/pmu.h>
32 pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec) in pmu_code() argument
38 nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu); in pmu_code()
41 nvkm_wr32(device, 0x10a188, (pmu + i) >> 8); in pmu_code()
52 pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len) in pmu_data() argument
58 nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu); in pmu_data()
87 struct nvbios_pmuR pmu; in pmu_load() local
89 if (!nvbios_pmuRm(bios, type, &pmu)) in pmu_load()
95 pmu_code(init, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false); in pmu_load()
96 pmu_code(init, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true); in pmu_load()
[all …]
/Linux-v5.4/tools/perf/util/
Dpmu.c21 #include "pmu.h"
24 #include "pmu-events/pmu-events.h"
79 * Reading/parsing the default pmu format definition, which should be
338 * event=0x0091 (read from files ../<PMU>/events/<FILE> in __perf_pmu__new_alias()
468 * Reading the pmu event aliases definition, which should be located at:
517 * Reading/parsing the default pmu type value, which should be
549 /* Add all pmus in sysfs to pmu list: */
637 * PMU CORE devices have different name other than cpu in sysfs on some
659 static char *perf_pmu__getcpuid(struct perf_pmu *pmu) in perf_pmu__getcpuid() argument
668 cpuid = get_cpuid_str(pmu); in perf_pmu__getcpuid()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/arm/samsung/
Dpmu.txt1 SAMSUNG Exynos SoC series PMU Registers
5 - "samsung,exynos3250-pmu" - for Exynos3250 SoC,
6 - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
7 - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
8 - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
9 - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
10 - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
11 - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
12 - "samsung,exynos5433-pmu" - for Exynos5433 SoC.
13 - "samsung,exynos7-pmu" - for Exynos7 SoC.
[all …]

12345678910>>...33