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/Linux-v6.1/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
159 #define DA9062AA_REVERT_SHIFT 7
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
[all …]
/Linux-v6.1/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
160 #define DA9150_WRITE_MODE_MASK BIT(6)
161 #define DA9150_REVERT_SHIFT 7
162 #define DA9150_REVERT_MASK BIT(7)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
180 #define DA9150_VDD33_SLEEP_MASK BIT(1)
181 #define DA9150_LFOSC_STAT_SHIFT 7
[all …]
/Linux-v6.1/drivers/net/dsa/microchip/
Dlan937x_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019-2021 Microchip Technology Inc.
10 /* 0 - Operation */
13 #define SW_PHY_REG_BLOCK BIT(7)
14 #define SW_FAST_MODE BIT(3)
15 #define SW_FAST_MODE_OVERRIDE BIT(2)
20 #define LUE_INT BIT(31)
21 #define TRIG_TS_INT BIT(30)
22 #define APB_TIMEOUT_INT BIT(29)
23 #define OVER_TEMP_INT BIT(28)
[all …]
Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
23 #define KSZ8863_PCS_RESET BIT(0)
27 #define SW_NEW_BACKOFF BIT(7)
28 #define SW_GLOBAL_RESET BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
31 #define SW_LINK_AUTO_AGING BIT(0)
35 #define SW_HUGE_PACKET BIT(6)
36 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
[all …]
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
[all …]
/Linux-v6.1/drivers/platform/x86/
Dmlx-platform.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
5 * Copyright (C) 2016-2018 Mellanox Technologies
6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
12 #include <linux/i2c-mux.h>
16 #include <linux/platform_data/i2c-mux-reg.h>
184 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0)
185 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3)
189 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0)
190 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1)
191 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2)
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
[all …]
/Linux-v6.1/include/linux/soundwire/
Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/Linux-v6.1/sound/soc/hisilicon/
Dhi6210-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
47 #define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN BIT(13)
[all …]
/Linux-v6.1/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
25 5.2.1 Parity checking and packet re-synchronization
33 7. Hardware version 4
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
118 calculating a parity bit for the last 3 bytes of each packet. The driver
145 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
173 ---------
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
[all …]
/Linux-v6.1/drivers/scsi/
DBusLogic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 Copyright 1995-1998 by Leonard N. Zubkoff <lnz@dandelion.com>
12 Special thanks to Wayne Yen, Jin-Lon Hon, and Alex Win of BusLogic, whose
60 #define BLOGIC_MIN_AUTO_TAG_DEPTH 7
91 #define BLOGIC_CCB_GRP_ALLOCSIZE 7
160 (adapter->adapter_type == BLOGIC_MULTIMASTER)
163 (adapter->adapter_type == BLOGIC_FLASHPOINT)
189 BLOGIC_VESA_BUS, /* BT-4xx */
190 BLOGIC_ISA_BUS, /* BT-5xx */
191 BLOGIC_MCA_BUS, /* BT-6xx */
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
24 PKT_TYPE_RX_EVENT = 7,
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/Linux-v6.1/drivers/net/wireless/ath/wil6210/
Dtxrx.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
[all …]
/Linux-v6.1/drivers/comedi/drivers/
Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/Linux-v6.1/drivers/gpu/drm/mediatek/
Dmtk_hdmi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define LR_SWAP BIT(0)
13 #define LFE_CC_SWAP BIT(1)
14 #define LSRS_SWAP BIT(2)
15 #define RLS_RRS_SWAP BIT(3)
16 #define LR_STATUS_SWAP BIT(4)
23 #define I2S_UV_V BIT(0)
24 #define I2S_UV_U BIT(1)
26 #define I2S_UV_CH_EN(x) BIT((x) + 2)
27 #define I2S_UV_TMDS_DEBUG BIT(6)
[all …]
/Linux-v6.1/drivers/media/i2c/
Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
128 #define DETECT_UTIL BIT(7) /* utility of HDMI level */
129 #define DETECT_HPD BIT(6) /* HPD of HDMI level */
130 #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */
131 #define DETECT_5V_B BIT(1) /* 5V present on input B */
132 #define DETECT_5V_A BIT(0) /* 5V present on input A */
135 #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */
[all …]
/Linux-v6.1/drivers/gpu/drm/bridge/analogix/
Danx7625.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 /* Loading OCM re-trying times */
50 #define INTR_SOFTWARE_INT BIT(3)
51 #define INTR_RECEIVED_MSG BIT(5)
63 #define STORE_AN BIT(7)
64 #define RX_REPEATER BIT(6)
65 #define RE_AUTHEN BIT(5)
66 #define SW_AUTH_OK BIT(4)
67 #define HARD_AUTH_EN BIT(3)
68 #define ENC_EN BIT(2)
[all …]
/Linux-v6.1/include/linux/mfd/
Dtps65218.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
63 #define TPS65218_INT1_VPRG BIT(5)
64 #define TPS65218_INT1_AC BIT(4)
65 #define TPS65218_INT1_PB BIT(3)
66 #define TPS65218_INT1_HOT BIT(2)
67 #define TPS65218_INT1_CC_AQC BIT(1)
68 #define TPS65218_INT1_PRGC BIT(0)
70 #define TPS65218_INT2_LS3_F BIT(5)
71 #define TPS65218_INT2_LS2_F BIT(4)
[all …]
/Linux-v6.1/drivers/net/ieee802154/
Dmcr20a.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
[all …]
/Linux-v6.1/drivers/ufs/host/
Dufs-renesas.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
19 #include "ufshcd-pltfrm.h"
62 PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
64 PARAM_POLL(0xd4, BIT(8), BIT(8))
71 PARAM_POLL(0xd4, BIT(8), BIT(8))
75 PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
77 PARAM_POLL(0xd4, BIT(8), BIT(8))
112 PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \
114 PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
165 PARAM_POLL(0xd4, BIT(8), BIT(8)),
[all …]
/Linux-v6.1/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/Linux-v6.1/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
[all …]
/Linux-v6.1/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
491 [F_CHGWDT_VAL] = REG_FIELD(WDT_STATUS, 0, 7),
501 [F_VIN_ORD] = REG_FIELD(VIN_CTRL_SET, 7, 7),
521 [F_CHG_EN] = REG_FIELD(CHGOP_SET2, 7, 7),
528 [F_VBUSCLPS_TH_SET] = REG_FIELD(VBUSCLPS_TH_SET, 7, 14),
529 [F_VCCCLPS_TH_SET] = REG_FIELD(VCCCLPS_TH_SET, 7, 14),
531 [F_WDT_PRE] = REG_FIELD(CHGWDT_SET, 0, 7),
533 [F_WDT_THERM] = REG_FIELD(BATTWDT_SET, 0, 7),
559 [F_IOUT_OUT_EN] = REG_FIELD(PMON_IOUT_CTRL_SET, 7, 7),
568 [F_VCC_USBDETEN] = REG_FIELD(VCC_UCD_SET, 7, 7),
[all …]
/Linux-v6.1/drivers/net/ipa/reg/
Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 /* Bits 5-31 reserved */
22 [CLKON_RX] = BIT(0),
23 [CLKON_PROC] = BIT(1),
24 [TX_WRAPPER] = BIT(2),
[all …]
/Linux-v6.1/include/linux/mfd/wcd934x/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
10 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(1)
19 #define WCD934X_EFUSE_SENSE_EN_MASK BIT(0)
20 #define WCD934X_EFUSE_SENSE_ENABLE BIT(0)
52 #define WCD934X_IRQ_EAR_PA_CNP_COMPLETE 7
82 #define WCD934X_ANA_BIAS_EN_MASK BIT(7)
83 #define WCD934X_ANA_BIAS_EN BIT(7)
84 #define WCD934X_ANA_PRECHRG_EN_MASK BIT(6)
85 #define WCD934X_ANA_PRECHRG_EN BIT(6)
[all …]

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