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/Linux-v5.15/include/linux/
Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
[all …]
Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
[all …]
/Linux-v5.15/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
/Linux-v5.15/lib/math/
Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
27 /* Not needed on 64bit architectures */
38 /* Reduce the thing a bit first */ in __div64_32()
43 rem -= (uint64_t) (high*base) << 32; in __div64_32()
[all …]
/Linux-v5.15/lib/
Datomic64_test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
[all …]
/Linux-v5.15/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
7 config 64BIT config
10 config 32BIT
42 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
50 select GENERIC_ATOMIC64 if !64BIT
64 select GENERIC_TIME_VSYSCALL if MMU && 64BIT
69 select HAVE_ARCH_KASAN if MMU && 64BIT
70 select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT
71 select HAVE_ARCH_KFENCE if MMU && 64BIT
[all …]
/Linux-v5.15/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
[all …]
Dcn23xx_vf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
47 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
69 /*------- Request Queue Macros ---------*/
85 /*------------------ Masks ----------------*/
[all …]
/Linux-v5.15/arch/x86/um/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
13 config 64BIT config
14 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
18 def_bool !64BIT
27 def_bool 64BIT
31 bool "Three-level pagetables" if !64BIT
32 default 64BIT
34 Three-level pagetables will let UML have more than 4G of physical
38 However, this it experimental on 32-bit architectures, so if unsure say
39 N (on x86-64 it's automatically enabled, instead, as it's safe there).
[all …]
/Linux-v5.15/drivers/gpio/
Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
31 #define XGPIO_GIER_IE BIT(31)
45 * struct xgpio_instance - Stores information about GPIO device
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
72 DECLARE_BITMAP(enable, 64);
[all …]
/Linux-v5.15/drivers/net/ethernet/broadcom/
Dtg3.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Copyright (C) 2007-2016 Broadcom Corporation.
9 * Copyright (C) 2016-2017 Broadcom Limited.
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
78 /* 0x04 --> 0x2c unused */
115 /* 0x30 --> 0x64 unused */
117 /* 0x66 --> 0x68 unused */
284 /* 0x94 --> 0x98 unused */
[all …]
/Linux-v5.15/arch/parisc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T if !64BIT
30 select GENERIC_ATOMIC64 if !64BIT
61 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
70 The PA-RISC microprocessor is designed by Hewlett-Packard and used
72 and later HP3000 series). The PA-RISC Linux project home page is
86 default "arch/parisc/configs/generic-32bit_defconfig" if !64BIT
87 default "arch/parisc/configs/generic-64bit_defconfig" if 64BIT
120 # unless you want to implement ACPI on PA-RISC ... ;-)
137 default 3 if 64BIT && PARISC_PAGE_SIZE_4KB
[all …]
/Linux-v5.15/drivers/acpi/acpica/
Dtbfadt.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: tbfadt - FADT table utilities
6 * Copyright (C) 2000 - 2021, Intel Corp.
143 * PARAMETERS: generic_address - GAS struct to be initialized
144 * space_id - ACPI Space ID for this register
145 * byte_width - Width of this register
146 * address - Address of the register
147 * register_name - ASCII name of the ACPI register
166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
[all …]
/Linux-v5.15/arch/s390/include/asm/
Delf.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Derived from "include/asm-i386/elf.h"
13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
[all …]
/Linux-v5.15/arch/s390/crypto/
Dcrc32be-vx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
9 * bit first (BE).
16 #include <asm/nospec-insn.h>
17 #include <asm/vx-insn.h>
19 /* Vector register range containing CRC-32 constants */
31 * The CRC-32 constant block contains reduction constants to fold and
34 * For the CRC-32 variants, the constants are precomputed according to
[all …]
/Linux-v5.15/include/xen/interface/
Dcallback.h36 * @extra_args == Operation-specific extra arguments (NULL if none).
45 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
59 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
60 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
61 * ('32-on-32-on-64', '32-on-64-on-64')
62 * [nb. also 64-bit guest applications on Intel CPUs
63 * ('64-on-64-on-64'), but syscall is preferred]
68 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
69 * ('32-on-32-on-64', '32-on-64-on-64')
93 * Not all callbacks can be unregistered. -EINVAL will be returned if
/Linux-v5.15/arch/x86/kvm/vmx/
Dvmx_ops.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 "16-bit accessor invalid for 64-bit field"); in vmcs_check16()
27 "16-bit accessor invalid for 64-bit high field"); in vmcs_check16()
29 "16-bit accessor invalid for 32-bit high field"); in vmcs_check16()
31 "16-bit accessor invalid for natural width field"); in vmcs_check16()
37 "32-bit accessor invalid for 16-bit field"); in vmcs_check32()
39 "32-bit accessor invalid for 64-bit field"); in vmcs_check32()
41 "32-bit accessor invalid for 64-bit high field"); in vmcs_check32()
43 "32-bit accessor invalid for natural width field"); in vmcs_check32()
49 "64-bit accessor invalid for 16-bit field"); in vmcs_check64()
[all …]
/Linux-v5.15/arch/mips/include/asm/
Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
20 /* The base address of the CM L2-only sync region */
24 * __mips_cm_phys_base - retrieve the physical base address of the CM
36 * mips_cm_is64 - determine CM register width
39 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
40 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
41 * or vice-versa. This variable indicates the width of the memory accesses
45 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
50 * mips_cm_error_report - Report CM cache errors
[all …]
/Linux-v5.15/Documentation/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
[all …]
/Linux-v5.15/drivers/infiniband/hw/bnxt_re/
Dqplib_sp.h2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
125 #define BNXT_QPLIB_ACCESS_LOCAL_WRITE BIT(0)
126 #define BNXT_QPLIB_ACCESS_REMOTE_READ BIT(1)
127 #define BNXT_QPLIB_ACCESS_REMOTE_WRITE BIT(2)
128 #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC BIT(3)
129 #define BNXT_QPLIB_ACCESS_MW_BIND BIT(4)
130 #define BNXT_QPLIB_ACCESS_ZERO_BASED BIT(5)
131 #define BNXT_QPLIB_ACCESS_ON_DEMAND BIT(6)
136 /* seq_err_naks_rcvd is 64 b */
[all …]
/Linux-v5.15/arch/mips/include/asm/octeon/
Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
[all …]
/Linux-v5.15/arch/mips/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
20 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
32 select GENERIC_ATOMIC64 if !64BIT
60 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
68 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
96 select MODULES_USE_ELF_RELA if MODULES && 64BIT
[all …]
/Linux-v5.15/arch/mips/kernel/
Dunaligned.c18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
96 #include "access-helper.h"
120 orig31 = regs->regs[31]; in emulate_load_store_insn()
132 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
173 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
182 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
203 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
[all …]
/Linux-v5.15/drivers/net/ethernet/cavium/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 depends on 64BIT && PCI
31 depends on 64BIT && PCI
37 depends on 64BIT && PCI
47 depends on 64BIT && PCI
56 depends on 64BIT && PCI
67 depends on 64BIT && PCI
93 depends on 64BIT && PCI_MSI
100 will be called liquidio_vf. MSI-X interrupt support is required
/Linux-v5.15/arch/x86/math-emu/
Dwm_shrx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 /*---------------------------------------------------------------------------+
6 | 64 bit right shift functions |
10 | Australia. E-mail billm@jacobi.maths.monash.edu.au |
17 +---------------------------------------------------------------------------*/
22 /*---------------------------------------------------------------------------+
27 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
29 | Forms a 96 bit quantity from the 64 bit arg and eax: |
30 | [ 64 bit arg ][ eax ] |
31 | shift right ---------> |
[all …]

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