Lines Matching +full:64 +full:- +full:bit
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
96 #include "access-helper.h"
120 orig31 = regs->regs[31]; in emulate_load_store_insn()
132 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
173 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
182 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
203 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
212 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
221 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
227 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
236 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
259 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
274 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
289 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
295 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
296 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
297 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
298 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
299 * instructions on 32-bit kernels. in emulate_load_store_insn()
308 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
312 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
318 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
319 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
320 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
321 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
322 * instructions on 32-bit kernels. in emulate_load_store_insn()
331 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
335 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
343 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
359 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
373 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
374 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
375 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
376 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
377 * instructions on 32-bit kernels. in emulate_load_store_insn()
383 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
390 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
405 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
437 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
544 regs->cp0_epc = origpc; in emulate_load_store_insn()
545 regs->regs[31] = orig31; in emulate_load_store_insn()
567 /* Recode table from 16-bit register notation to 32-bit GPR. */
570 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
589 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
590 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
597 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
600 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
607 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
657 regs->regs[reg] = value; in emulate_load_store_microMIPS()
662 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
673 value = regs->regs[reg]; in emulate_load_store_microMIPS()
678 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
696 regs->regs[reg] = value; in emulate_load_store_microMIPS()
701 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
716 value = regs->regs[reg]; in emulate_load_store_microMIPS()
721 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
744 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
749 regs->regs[i] = value; in emulate_load_store_microMIPS()
756 regs->regs[30] = value; in emulate_load_store_microMIPS()
762 regs->regs[31] = value; in emulate_load_store_microMIPS()
780 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
781 value = regs->regs[i]; in emulate_load_store_microMIPS()
788 value = regs->regs[30]; in emulate_load_store_microMIPS()
795 value = regs->regs[31]; in emulate_load_store_microMIPS()
818 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
823 regs->regs[i] = value; in emulate_load_store_microMIPS()
830 regs->regs[30] = value; in emulate_load_store_microMIPS()
836 regs->regs[31] = value; in emulate_load_store_microMIPS()
859 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
860 value = regs->regs[i]; in emulate_load_store_microMIPS()
867 value = regs->regs[30]; in emulate_load_store_microMIPS()
874 value = regs->regs[31]; in emulate_load_store_microMIPS()
919 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
920 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
926 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
975 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
980 regs->regs[i] = value; in emulate_load_store_microMIPS()
985 regs->regs[31] = value; in emulate_load_store_microMIPS()
995 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
996 value = regs->regs[i]; in emulate_load_store_microMIPS()
1002 value = regs->regs[31]; in emulate_load_store_microMIPS()
1052 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1062 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1072 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1078 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1079 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1080 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1081 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1082 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1090 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1094 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1100 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1101 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1102 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1103 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1104 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1112 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1116 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1123 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1133 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1142 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1143 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1144 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1145 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1146 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1151 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1158 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1162 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1171 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1172 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1207 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1208 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1314 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1325 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1338 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1344 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1345 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1346 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1347 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1348 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1357 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1361 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1368 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1369 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1370 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1371 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1372 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1381 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1385 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1393 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1401 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1406 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1416 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1417 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1418 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1419 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1420 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1426 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1433 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1452 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1453 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1482 1, regs, regs->cp0_badvaddr); in do_ade()
1486 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1502 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1505 * 16-bit mode? in do_ade()
1507 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1514 (void __user *)regs->cp0_badvaddr); in do_ade()
1520 (void __user *)regs->cp0_badvaddr); in do_ade()
1531 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()