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/Linux-v5.15/arch/powerpc/boot/dts/fsl/
Dpq3-dma-1.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
39 reg = <0xc300 0x4>;
40 ranges = <0x0 0xc100 0x200>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <76 2 0 0>;
50 reg = <0x80 0x80>;
52 interrupts = <77 2 0 0>;
56 reg = <0x100 0x80>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/interconnect/
Dqcom,sdm660.yaml124 reg = <0x01008000 0x78000>;
133 reg = <0x01500000 0x10000>;
142 reg = <0x01626000 0x7090>;
151 reg = <0x01704000 0xc100>;
171 reg = <0x01745000 0xa010>;
181 reg = <0x17900000 0xe000>;
/Linux-v5.15/drivers/dma/ti/
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/Linux-v5.15/arch/arm/mach-s5pv210/
Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
[all …]
/Linux-v5.15/include/scsi/
Dscsi.h26 #define SCSI_MAX_PROT_SG_SEGMENTS 0xFFFF
32 #define SCAN_WILD_CARD ~0
56 #define SCSI_W_LUN_BASE 0xc100
63 return (lun & 0xff00) == SCSI_W_LUN_BASE; in scsi_is_wlun()
76 if (status < 0) in scsi_status_is_check_condition()
78 status &= 0xfe; in scsi_status_is_check_condition()
85 #define EXTENDED_MODIFY_DATA_POINTER 0x00
86 #define EXTENDED_SDTR 0x01
87 #define EXTENDED_EXTENDED_IDENTIFY 0x02 /* SCSI-I only */
88 #define EXTENDED_WDTR 0x03
[all …]
/Linux-v5.15/drivers/mfd/
Dqcom-pm8008.c20 #define I2C_INTR_STATUS_BASE 0x0550
21 #define INT_RT_STS_OFFSET 0x10
22 #define INT_SET_TYPE_OFFSET 0x11
23 #define INT_POL_HIGH_OFFSET 0x12
24 #define INT_POL_LOW_OFFSET 0x13
25 #define INT_LATCHED_CLR_OFFSET 0x14
26 #define INT_EN_SET_OFFSET 0x15
27 #define INT_EN_CLR_OFFSET 0x16
28 #define INT_LATCHED_STS_OFFSET 0x18
38 #define PM8008_PERIPH_0_BASE 0x900
[all …]
/Linux-v5.15/drivers/scsi/
D3w-xxxx.h62 [0x000] = "INFO: AEN queue empty",
63 [0x001] = "INFO: Soft reset occurred",
64 [0x002] = "ERROR: Unit degraded: Unit #",
65 [0x003] = "ERROR: Controller error",
66 [0x004] = "ERROR: Rebuild failed: Unit #",
67 [0x005] = "INFO: Rebuild complete: Unit #",
68 [0x006] = "ERROR: Incomplete unit detected: Unit #",
69 [0x007] = "INFO: Initialization complete: Unit #",
70 [0x008] = "WARNING: Unclean shutdown detected: Unit #",
71 [0x009] = "WARNING: ATA port timeout: Port #",
[all …]
D3w-9xxx.h58 {0x0000, "AEN queue empty"},
59 {0x0001, "Controller reset occurred"},
60 {0x0002, "Degraded unit detected"},
61 {0x0003, "Controller error occurred"},
62 {0x0004, "Background rebuild failed"},
63 {0x0005, "Background rebuild done"},
64 {0x0006, "Incomplete unit detected"},
65 {0x0007, "Background initialize done"},
66 {0x0008, "Unclean shutdown detected"},
67 {0x0009, "Drive timeout detected"},
[all …]
/Linux-v5.15/arch/powerpc/boot/dts/
Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/Linux-v5.15/drivers/scsi/ufs/
Dufs.h30 * UFS device may have standard LUs and LUN id could be from 0x00 to
31 * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
33 * which again could be from 0x00 to 0x7F. For W-LUs, device only use
35 * from 0xc100 (SCSI_W_LUN_BASE) onwards.
36 * This means max. LUN number reported from UFS device could be 0xC17F.
38 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
41 #define UFS_RPMB_UNIT 0xC4
43 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
48 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
49 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/Linux-v5.15/sound/soc/codecs/
Drt1308-sdw.c30 case 0x00e0: in rt1308_readable_register()
31 case 0x00f0: in rt1308_readable_register()
32 case 0x2f01 ... 0x2f07: in rt1308_readable_register()
33 case 0x3000 ... 0x3001: in rt1308_readable_register()
34 case 0x3004 ... 0x3005: in rt1308_readable_register()
35 case 0x3008: in rt1308_readable_register()
36 case 0x300a: in rt1308_readable_register()
37 case 0xc000 ... 0xcff3: in rt1308_readable_register()
47 case 0x2f01 ... 0x2f07: in rt1308_volatile_register()
48 case 0x3000 ... 0x3001: in rt1308_volatile_register()
[all …]
/Linux-v5.15/drivers/usb/dwc3/
Dcore.h48 #define DWC3_EVENT_TYPE_MASK 0xfe
50 #define DWC3_EVENT_TYPE_DEV 0
54 #define DWC3_DEVICE_EVENT_DISCONNECT 0
67 #define DWC3_OTG_ROLE_IDLE 0
71 #define DWC3_GEVNTCOUNT_MASK 0xfffc
73 #define DWC3_GSNPSID_MASK 0xffff0000
74 #define DWC3_GSNPSREV_MASK 0xffff
78 #define DWC3_XHCI_REGS_START 0x0
79 #define DWC3_XHCI_REGS_END 0x7fff
80 #define DWC3_GLOBALS_REGS_START 0xc100
[all …]
/Linux-v5.15/drivers/comedi/drivers/
Dadv_pci1710.c42 #define PCI171X_AD_DATA_REG 0x00 /* R: A/D data */
43 #define PCI171X_SOFTTRG_REG 0x00 /* W: soft trigger for A/D */
44 #define PCI171X_RANGE_REG 0x02 /* W: A/D gain/range register */
47 #define PCI171X_RANGE_GAIN(x) (((x) & 0x7) << 0)
48 #define PCI171X_MUX_REG 0x04 /* W: A/D multiplexor control */
49 #define PCI171X_MUX_CHANH(x) (((x) & 0xff) << 8)
50 #define PCI171X_MUX_CHANL(x) (((x) & 0xff) << 0)
52 #define PCI171X_STATUS_REG 0x06 /* R: status register */
57 #define PCI171X_CTRL_REG 0x06 /* W: control register */
58 #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */
[all …]
/Linux-v5.15/drivers/clk/imx/
Dclk-imx8mq.c299 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
309 base = of_iomap(np, 0); in imx8mq_clocks_probe()
314 …hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
315 …hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
316 …hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, … in imx8mq_clocks_probe()
317 …hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
318 …hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_s… in imx8mq_clocks_probe()
319 …hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_… in imx8mq_clocks_probe()
320 …hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
321 …hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sel… in imx8mq_clocks_probe()
[all …]
Dclk-imx8mp.c412 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
418 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
441 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
442 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
443 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
444 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
445 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
446 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
447 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
/Linux-v5.15/include/linux/
Data.h22 #define ATA_DMA_BOUNDARY 0xffffUL
23 #define ATA_DMA_MASK 0xffffffffULL
38 ATA_ID_CONFIG = 0,
104 ATA_PIO0 = (1 << 0),
114 ATA_SWDMA0 = (1 << 0),
120 ATA_MWDMA0 = (1 << 0),
129 ATA_UDMA0 = (1 << 0),
150 ATA_DMA_CMD = 0,
152 ATA_DMA_START = (1 << 0),
155 ATA_DMA_ACTIVE = (1 << 0),
[all …]

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